category: System-Level Design

category: IoT, Security & Automotive

The Drive Toward Virtual Prototypes
By Brian Bailey - 22 Nov, 2022 - Comments: 1

Chipmakers are piling an increasing set of demands on virtual prototypes that go well beyond its original scope, forcing EDA companies to significantly rethink models, abstractions, interfaces, view orthogonality, and flows. The virtual prototype has been around for at least 20 years, but its role has been limited. It has largely been used as an integration and analysis platform for models t... » read more

Being A Design Verification Engineer Is Fun And Rewarding
By Lauranne Choquin - 22 Nov, 2022 - Comments: 0

Philippe Luc, director of verification at Codasip, talked to students of the UK Electronics Skills Foundation (UKESF) about what it is like to be a verification engineer. On one hand the UKESF encourages young people to study electronics and pursue careers in this sector, and on the other hand Codasip is very keen to help prepare the engineers who will solve tomorrow’s technology chall... » read more

Week In Review: Design, Low Power
By Marie C. Baca - 18 Nov, 2022 - Comments: 0

Tools and IP Cadence announced that its IP for GDDR6 is now silicon-proven for TSMC’s N5 process technology. The IP consists of Cadence PHY,  controller design IP, and verification IP (VIP), and is targeted for very high-bandwidth memory applications. “The improved PHY and controller design IP for GDDR6 with DRAM data rates at 22Gbps in the TSMC N5 process is the fastest of the GDDR6 fami... » read more

Blog Review: Nov. 16
By Jesse Allen - 16 Nov, 2022 - Comments: 0

Siemens EDA's Jake Wiltgen explains the difference between transient and permanent faults when designing to the ISO 26262 standard, including where they come from and key ways to protect against them. Synopsys' Vikas Gautam points to how the economics of designing large SoCs is driving chiplet-based designs and the need for die-to-die standards such as UCIe, along with the key protocol verif... » read more

Ensuring Memory Reliability Throughout the Silicon Lifecycle
By Anand Thiruvengadam - 14 Nov, 2022 - Comments: 0

By Anand Thiruvengadam and Guy Cortez Memories are everywhere in modern electronics. Discrete memory chips account for much of the space on printed circuit boards (PCBs). Embedded memories consume much of the floorplan in system-on-chip (SoC) devices. Many multi-die chip configurations, including 2.5D/3DIC devices, are driven by the need for faster memory access. Designing and verifying memo... » read more

Week In Review: Design, Low Power
By Jesse Allen - 11 Nov, 2022 - Comments: 0

Chip design Fraunhofer IIS/EAS implemented the Bunch of Wires (BoW) standard-based interface IP from the Open Compute Project (OCP) on Samsung's 5nm technology. The effort is intended to make chiplets more feasible for products with small and medium-sized production runs and determine the need for additional uniform standards in the future, such as for die-to-die bonding. “As part of t... » read more

Blog Review: Nov. 9
By Jesse Allen - 09 Nov, 2022 - Comments: 0

Cadence's Claire Ying finds that the latest update to CXL, which introduced memory-centric fabric architectures and expanded capabilities for improving scale and optimizing resource utilization, could change how some of the world’s largest data centers and fastest supercomputers are built. Synopsys' Gervais Fong and Morten Christiansen examine the latest updates in the USB 80Gbps specifica... » read more

Week In Review: Design, Low Power
By Marie C. Baca - 04 Nov, 2022 - Comments: 0

Earnings and Acquisitions Siemens will acquire Avery Design Systems, a simulation-independent verification IP supplier, in the first quarter of fiscal year 2023. The terms of the transaction were not disclosed. Siemens executives say the acquisition will “enhance Siemens’ offerings across mainstream verification IP segments, while further extending Siemens verification solutions into area... » read more

Blog Review: Nov. 2
By Jesse Allen - 02 Nov, 2022 - Comments: 0

Siemens EDA's Harry Foster examines how successful FPGA projects are in terms of verification effectiveness, finding that only 16% of all FPGA projects were able to achieve no non-trivial bug escapes into production, worse than IC/ASIC in terms of first silicon success. Synopsys' Jamie Boote and The Chertoff Group's David London break down best practice guidance and directives U.S. governmen... » read more

Chip Design Shifts As Fundamental Laws Run Out Of Steam
By Ann Mutschler - 31 Oct, 2022 - Comments: 12

Dennard scaling is gone, Amdahl's Law is reaching its limit, and Moore's Law is becoming difficult and expensive to follow, particularly as power and performance benefits diminish. And while none of that has reduced opportunities for much faster, lower-power chips, it has significantly shifted the dynamics for their design and manufacturing. Rather than just different process nodes and half ... » read more

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