Chip Industry Week In Review

By The SE Staff - 08 Sep, 2023 - Comments: 0

By Liz Allan, Jesse Allen, and Karen Heyman Global semiconductor equipment billings dipped 2% year-over-year to US$25.8 billion in Q2, and slipped 4% compared with Q1, according to SEMI. Similarly, the top 10 semiconductor foundries reported a 1.1% quarterly-over-quarter revenue decline in Q2. A rebound is anticipated in Q3, according to TrendForce. Synopsys extended its AI-driven EDA ... » read more

Blog Review: September 6

By Jesse Allen - 06 Sep, 2023 - Comments: 0

Cadence's Reela Samuel listens in as industry experts discuss whether generative AI-powered tools could facilitate the creation of diverse chip types and address talent shortages by creating a more accessible entry point for those interested in circuit, chip, or system design. Synopsys' Ian Land, Jigesh Patel, and Kenneth Larsen find that the way that today’s government, aerospace, and d... » read more

Performance & Efficiency Cores For Servers

By Barry Pangrle - 31 Aug, 2023 - Comments: 0

HotChips 2023 was held August 27-29, 2023 at Stanford University in California and was the first in-person version of the conference in 4 years. The conference was held in a hybrid format that had over 500 participants in-person and over 1,000 attending virtually online. Topics covered a broad range of advancements in computing, connectivity, and computer architecture. Both AMD and Intel gav... » read more

Challenges In Ramping New Manufacturing Processes

By Ed Sperling - 30 Aug, 2023 - Comments: 0

Despite a slowdown for Moore’s Law, there are more new manufacturing processes rolling out faster than ever before. The challenge now is to decrease time to yield, which involves everything from TCAD and design technology co-optimization, to refinement of power, performance, area/cost, and process control and analytics. Srinivas Raghvendra, vice president of engineering at Synopsys, talks abo... » read more

Blog Review: August 30

By Jesse Allen - 30 Aug, 2023 - Comments: 0

Siemens' Dan Yu examines hallucinations in large language models, the Universal Approximation Theorem, and the role they play in applying LLMs to EDA. Cadence's Mamta Rana introduces shared flow control in PCIe 6.0, which enables the reduced cost implementation of multiple virtual channels by allowing common sets of resources to be shared. Synopsys' Arturo Salz and Johannes Stahl note tha... » read more

New Concepts Required For Security Verification

By Brian Bailey - 28 Aug, 2023 - Comments: 0

Verification for security requires new practices in both the development and verification flows, but tools and methodologies to enable this are rudimentary today. Flows are becoming more complex, especially when they span multiple development groups. Security is special in that it is pervasive throughout the development process, requiring both positive and negative verification. Positive ver... » read more

Week In Review: Design, Low Power

By Linda Christensen - 25 Aug, 2023 - Comments: 0

Arm filed its registration statement for a highly anticipated IPO. Chip industry heavyweights Apple, Samsung, NVIDIA, and Intel are all expected to invest. Find the SEC filing here. Taiwan’s National Science and Technology Council (NSTC) laid out a 10-year initiative to bolster its IC design market share to 40% worldwide by 2033, with the first year’s budget of US $376 million. The sh... » read more

Predicting The Future For Semiconductors

By Brian Bailey - 24 Aug, 2023 - Comments: 1

Is it possible to predict the future? Of course not. We all make projections of what happened in the past, where they are now, and the implications for the future. We bias that in various ways and think we are making some astounding revelation, which is highly unlikely to become true. Of course, by luck, some people get it right and they are bestowed with grand accolades and awards. The likelih... » read more

Balancing IR Drop Unpredictability With Post-Silicon Flexibility

By Aakash Jani - 24 Aug, 2023 - Comments: 0

The concept of IR drop in silicon chips has always been a crucial aspect of chip design. However, recent technological trends and the emergence of new challenges, such as voltage-sensitive paths, have introduced a degree of uncertainty in predicting and effectively managing IR drop. These uncertainties are driving the need for a more flexible approach in mitigating on-die voltage droop. Increa... » read more

Design Complexity In The Golden Age Of Semiconductors

By Frank Schirrmeister - 24 Aug, 2023 - Comments: 0

While writing last month's blog that used some of the trend charts we have seen, I noticed that a lot of the data ends in 2020 or earlier, but I was too close to the deadline to sit down and make orderly updates to some of the charts. Working day-to-day in the area of SoC integration and networks-on-chips (NoCs), the classic chart based on Karl Rupp's now 50 years of processor data that overlay... » read more

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