Quantum Computing Architecture Enabling Communication Between Superconducting Quantum Processors (MIT)


A technical paper titled "On-demand directional microwave photon emission using waveguide quantum electrodynamics" was published by researchers at MIT. “Quantum interconnects are a crucial step toward modular implementations of larger-scale machines built from smaller individual components,” says Bharath Kannan PhD ’22, co-lead author of a research paper describing this technique, in a... » read more

Arbitrary Precision DNN Accelerator Controlled by a RISC-V CPU (Ecole Polytechnique Montreal, IBM, Mila, CMC)


A new technical paper titled "BARVINN: Arbitrary Precision DNN Accelerator Controlled by a RISC-V CPU" was written by researchers at Ecole Polytechnique Montreal, IBM, Mila and CMC Microsystems. It was accepted for publication in the 2023, 28th Asia and South Pacific Design Automation Conference (ASP-DAC 2023) in Japan. Abstract: "We present a DNN accelerator that allows inference at arbitr... » read more

FPGA-Based Prototyping Framework For Processing In DRAM (ETH Zurich & TOBB Univ.)


A technical paper titled "PiDRAM: A Holistic End-to-end FPGA-based Framework for Processing-in-DRAM" was published by researchers at ETH Zurich and TOBB University of Economics and Technology. Abstract "Processing-using-memory (PuM) techniques leverage the analog operation of memory cells to perform computation. Several recent works have demonstrated PuM techniques in off-the-shelf DRAM dev... » read more

Graphene-Based Electronics (Georgia Tech)


A technical paper titled "An epitaxial graphene platform for zero-energy edge state nanoelectronics" was published by researchers at Georgia Tech, Tianjin University, CNRS, Synchrotron SOLEIL, National High Magnetic Field Laboratory and others. “Graphene’s power lies in its flat, two-dimensional structure that is held together by the strongest chemical bonds known,” said Walter de Heer... » read more

MTJ-based Circuits Provide Low-Cost, Energy Efficient Solution For Future Hardware Implementation in SC Algorithms


A review paper titled "Review of Magnetic Tunnel Junctions for Stochastic Computing" was published by researchers at University of Minnesota Twin Cities. Funding agencies include Semiconductor Research Corporation (SRC), CAPSL, NIST, DARPA and others. Abstract: "Modern computing schemes require large circuit areas and large energy consumption for neuromorphic computing applications, such as... » read more

Rowhammer Mitigation: In-DRAM Mechanism Scaling The Number of Refreshes With Activations (ETH Zurich)


A technical paper titled "REGA: Scalable Rowhammer Mitigation with Refresh-Generating Activations" was written by researchers at Computer Security Group (COMSEC), ETH Zurich and Zentel Japan. The paper will be presented at IEEE's Symposium on Security and Privacy in May 2023. "With REGA, we propose the first fully in-DRAM mitigation capable of protecting devices independently from their blas... » read more

Hardware Accelerator For Fully Homomorphic Encryption


A technical paper titled "CraterLake: A Hardware Accelerator for Efficient Unbounded Computation on Encrypted Data" was published by researchers at MIT, IBM TJ Watson, SRI International, and University of Michigan. "We present CraterLake, the first FHE accelerator that enables FHE programs of unbounded size (i.e., unbounded multiplicative depth). Such computations require very large cipherte... » read more

Repurposing Josephson Junctions At The Cell Boundaries For Fan-out (UCSB)


A technical paper titled "Low-Cost Superconducting Fan-Out with Repurposed Josephson Junctions" was published by researchers at UC Santa Barbara.  The paper received an award at the Applied Superconductivity Conference in Oct 2022 and was highlighted in this UCSB news article. Abstract: "Superconductor electronics (SCE) promise computer systems with orders of magnitude higher speeds and lo... » read more

Automatic Layout Generator Targeting Region-based Layouts for Advanced FinFET-Based Full-Custom Circuits (UT Austin/NVIDIA)


A technical paper titled "AutoCRAFT: Layout Automation for Custom Circuits in Advanced FinFET Technologies" was published by researchers at UT Austin and NVIDIA. "This paper presents AutoCRAFT, an automatic layout generator targeting region-based layouts for advanced FinFET-based full-custom circuits. AutoCRAFT uses specialized place-and-route (P&R) algorithms to handle various design cons... » read more

Step Towards A 5G Software-Defined RAN Over A Fully Open-Source Parallel RISC-V Architecture (ETH Zurich)


A technical paper titled "Efficient Parallelization of 5G-PUSCH on a Scalable RISC-V Many-core Processor" was published by researchers at ETH Zurich. Abstract (partial) "5G Radio access network disaggregation and softwarization pose challenges in terms of computational performance to the processing units. At the physical layer level, the baseband processing computational effort is typicall... » read more

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