category: Architectures

category: IoT, Security & Automotive

Memory-Computation Decoupling Execution To Achieve Ideal All-Bank PIM Performance
By Technical Paper Link - 18 Oct, 2022 - Comments: 0

A new technical paper titled "Achieving the Performance of All-Bank In-DRAM PIM With Standard Memory Interface: Memory-Computation Decoupling" was published by researchers at Korea University. "This paper proposed the memory-computation decoupled PIM architecture to provide the performance comparable to the all-bank PIM while preserving the standard DRAM interface, i.e., DRAM commands, powe... » read more

A Full-Stack Domain-Specific Overlay Generation Framework Verified On FPGA
By Technical Paper Link - 12 Oct, 2022 - Comments: 0

A new technical paper titled "OverGen: Improving FPGA Usability through Domain-specific Overlay Generation" by researchers at UCLA and Chinese Academy of Sciences. "Our essential idea is to develop a hardware generation framework targeting a highly-customizable overlay, so that the abstraction gap can be lowered by tuning the design instance to applications of interest. We leverage and ext... » read more

Transistor-Free Compute-In-Memory Architecture
By Technical Paper Link - 11 Oct, 2022 - Comments: 0

A new technical paper titled "Reconfigurable Compute-In-Memory on Field-Programmable Ferroelectric Diodes" was recently published by researchers at University of Pennsylvania, Sandia National Labs, and Brookhaven National Lab. The compute-in-memory design is different as it is completely transistor-free. “Even when used in a compute-in-memory architecture, transistors compromise the access... » read more

Accelerating Off-Chip Load Requests By Removing The On-Chip Cache Access Latency From Their Critical Path
By Technical Paper Link - 11 Oct, 2022 - Comments: 0

A new technical paper titled "Hermes: Accelerating Long-Latency Load Requests via Perceptron-Based Off-Chip Load Prediction" was published by researchers at ETH Zurich, Intel Processor Architecture Research Lab, and LIRMM, Univ. Montpellier, CNRS.  The work received a best paper award at MICRO 2022. Abstract "Long-latency load requests continue to limit the performance of high-performance ... » read more

Adaptive Memristive Hardware
By Technical Paper Link - 02 Oct, 2022 - Comments: 0

A new technical paper titled "Self-organization of an inhomogeneous memristive hardware for sequence learning" was just published by researchers at University of Zurich, ETH Zurich, Université Grenoble Alpes, CEA, Leti and Toshiba. "We design and experimentally demonstrate an adaptive hardware architecture Memristive Self-organizing Spiking Recurrent Neural Network (MEMSORN). MEMSORN incorp... » read more

Framework Based on an RISC-V Microprocessor Supporting LiM Operations
By Technical Paper Link - 29 Sep, 2022 - Comments: 0

A new technical paper titled "RISC-Vlim, a RISC-V Framework for Logic-in-Memory Architectures" was published by researchers at Politecnico di Torino (Italy), Univerity of Tor Vergata (Italy), and University of Twente (The Netherlands). Abstract: "Most modern CPU architectures are based on the von Neumann principle, where memory and processing units are separate entities. Although processin... » read more

Decreasing Refresh Latency of Off-the-Shelf DRAM Chips
By Technical Paper Link - 28 Sep, 2022 - Comments: 0

A new technical paper titled "HiRA: Hidden Row Activation for Reducing Refresh Latency of Off-the-Shelf DRAM Chips" was published by researchers at ETH Zürich, TOBB University of Economics and Technology and Galicia Supercomputing Center (CESGA). Abstract "DRAM is the building block of modern main memory systems. DRAM cells must be periodically refreshed to prevent data loss. Refresh oper... » read more

Cybersecurity & FPGA Devices
By Technical Paper Link - 28 Sep, 2022 - Comments: 0

A technical paper titled "A Survey on FPGA Cybersecurity Design Strategies" is presented by researchers at Université Laval, Canada. Abstract (partial): "This paper presents a critical literature review on the security aspects of field programmable gate array (FPGA) devices. FPGA devices present unique challenges to cybersecurity through their reconfigurable nature. This paper also pays sp... » read more

FP8: Cross-Industry Hardware Specification For AI Training And Inference (Arm, Intel, Nvidia)
By Technical Paper Link - 16 Sep, 2022 - Comments: 0

Arm, Intel, and Nvidia proposed a specification for an 8-bit floating point (FP8) format that could provide a common interchangeable format that works for both AI training and inference and allow AI models to operate and perform consistently across hardware platforms. Find the technical paper titled " FP8 Formats For Deep Learning" here. Published Sept 2022. Abstract: "FP8 is a natural p... » read more

Setting The Memory Controller Free From Managing DRAM Maintenance Ops (ETH Zurich)
By Technical Paper Link - 14 Sep, 2022 - Comments: 0

A new technical paper titled "A Case for Self-Managing DRAM Chips: Improving Performance, Efficiency, Reliability, and Security via Autonomous in-DRAM Maintenance Operations" was published by researchers at ETH Zurich. Abstract: "The rigid interface of current DRAM chips places the memory controller completely in charge of DRAM control. Even DRAM maintenance operations, which are used to en... » read more

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