category: Architectures

category: IoT, Security & Automotive

CXL-Based Memory Pooling System Meets Cloud Performance Goals And Significantly Reduces DRAM Cost
By Technical Paper Link - 05 Mar, 2023 - Comments: 0

A technical paper titled "Pond: CXL-Based Memory Pooling Systems for Cloud Platforms" was published by researchers at Virginia Tech, Intel, Microsoft Azure, Google, and Stone Co. Abstract "Public cloud providers seek to meet stringent performance requirements and low hardware cost. A key driver of performance and cost is main memory. Memory pooling promises to improve DRAM utilization and t... » read more

Using Formal Verification To Optimize HLS-Produced Circuits (ETH Zurich)
By Technical Paper Link - 05 Mar, 2023 - Comments: 0

A new technical paper titled "Eliminating Excessive Dynamism of Dataflow Circuits Using Model Checking" was published by researchers at ETH Zurich. Abstract "Recent HLS efforts explore the generation of dynamically scheduled, dataflow circuits from high-level code; their ability to adapt the schedule at runtime to particular data and control outcomes promises superior performance to standar... » read more

Fast Parallel Multi-HDL Compiler (UC Santa Cruz)
By Technical Paper Link - 04 Mar, 2023 - Comments: 0

A technical paper titled "A Multi-threaded Fast Hardware Compiler for HDL" was published by researchers at UC Santa Cruz. Abstract: "A set of new Hardware Description Languages (HDLs) are emerging to ease hardware design. HDL compilation time is a major bottleneck in the designer’s productivity. Moreover, as the HDLs are developed independently, the possibility to share innovations in com... » read more

Energy-Efficient Execution Scheme For Dynamic Neural Networks on Heterogeneous MPSoCs
By Technical Paper Link - 04 Mar, 2023 - Comments: 0

A technical paper titled "Map-and-Conquer: Energy-Efficient Mapping of Dynamic Neural Nets onto Heterogeneous MPSoCs" was published (preprint) by researchers at LAMIH/UMR CNRS, Universite Polytechnique Hauts-de-France and UC Irvine. Abstract "Heterogeneous MPSoCs comprise diverse processing units of varying compute capabilities. To date, the mapping strategies of neural networks (NNs) onto ... » read more

Asynchronously Parallel Optimization Method For Sizing Analog Transistors Using Deep Neural Network Learning
By Technical Paper Link - 03 Mar, 2023 - Comments: 0

A new technical paper titled "APOSTLE: Asynchronously Parallel Optimization for Sizing Analog Transistors Using DNN Learning" was published by researchers at UT Austin and Analog Devices. Abstract "Analog circuit sizing is a high-cost process in terms of the manual effort invested and the computation time spent. With rapidly developing technology and high market demand, bringing automated s... » read more

Review of Methods to Design Secure Memristor Computing Systems
By Technical Paper Link - 27 Feb, 2023 - Comments: 0

A technical paper titled "Review of security techniques for memristor computing systems" was published by researchers at Israel Institute of Technology, Friedrich Schiller University Jena (Germany), and Leibniz Institute of Photonic Technology (IPHT). Abstract "Neural network (NN) algorithms have become the dominant tool in visual object recognition, natural language processing, and robotic... » read more

Security-Aware Compiler-Assisted Countermeasure to Mitigate Fault Attacks on RISC-V
By Technical Paper Link - 26 Feb, 2023 - Comments: 0

A new technical paper titled "CompaSeC: A Compiler-Assisted Security Countermeasure to Address Instruction Skip Fault Attacks on RISC-V" was published by researchers at TU Munich and Fraunhofer Institute for Applied and Integrated Security (AISEC). Abstract "Fault-injection attacks are a risk for any computing system executing security-relevant tasks, such as a secure boot process. While ha... » read more

Index-Based Multi-Core BDD Package With Dynamic Memory Management & Reduced Fragmentation
By Technical Paper Link - 26 Feb, 2023 - Comments: 0

A technical paper titled "EDDY: A Multi-Core BDD Package with Dynamic Memory Management and Reduced Fragmentation" was published by researchers at University of Bremen. ABSTRACT "In recent years, hardware systems have significantly grown in complexity. Due to the increasing complexity, there is a need to continuously improve the quality of the hardware design process. This leads designers t... » read more

In-Memory Computing: Assessing Multilevel RRAM-Based VMM Operations
By Technical Paper Link - 26 Feb, 2023 - Comments: 0

A new technical paper titled "Experimental Assessment of Multilevel RRAM-Based Vector-Matrix Multiplication Operations for In-Memory Computing" was published by researchers at IHP (the Leibniz Institute for High Performance Microelectronics). Abstract: "Resistive random access memory (RRAM)-based hardware accelerators are playing an important role in the implementation of in-memory computin... » read more

A RISC-V On-Chip Parallel Power Controller for HPC (ETH Zurich, U. of Bologna)
By Technical Paper Link - 26 Feb, 2023 - Comments: 0

A new technical paper titled "ControlPULP: A RISC-V On-Chip Parallel Power Controller for Many-Core HPC Processors with FPGA-Based Hardware-In-The-Loop Power and Thermal Emulation" was published (preprint) by researchers at ETH Zurich and University of Bologna. Abstract (partial) "High-Performance Computing (HPC) processors are nowadays integrated Cyber-Physical Systems demanding complex an... » read more

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