category: Architectures

category: IoT, Security & Automotive

FP8: Cross-Industry Hardware Specification For AI Training And Inference (Arm, Intel, Nvidia)
By Technical Paper Link - 16 Sep, 2022 - Comments: 0

Arm, Intel, and Nvidia proposed a specification for an 8-bit floating point (FP8) format that could provide a common interchangeable format that works for both AI training and inference and allow AI models to operate and perform consistently across hardware platforms. Find the technical paper titled " FP8 Formats For Deep Learning" here. Published Sept 2022. Abstract: "FP8 is a natural p... » read more

Setting The Memory Controller Free From Managing DRAM Maintenance Ops (ETH Zurich)
By Technical Paper Link - 14 Sep, 2022 - Comments: 0

A new technical paper titled "A Case for Self-Managing DRAM Chips: Improving Performance, Efficiency, Reliability, and Security via Autonomous in-DRAM Maintenance Operations" was published by researchers at ETH Zurich. Abstract: "The rigid interface of current DRAM chips places the memory controller completely in charge of DRAM control. Even DRAM maintenance operations, which are used to en... » read more

New Method of Comparing Neural Networks (Los Alamos National Lab)
By Technical Paper Link - 13 Sep, 2022 - Comments: 0

A new research paper titled "If You’ve Trained One You’ve Trained Them All: Inter-Architecture Similarity Increases With Robustness" from researchers at Los Alamos National Laboratory (LANL) and was recently presented at the Conference on Uncertainty in Artificial Intelligence. The team developed a new approach for comparing neural networks and "applied their new metric of network simila... » read more

Hardware Implementation Of A Random Gumber Generator On A FPGA
By Technical Paper Link - 13 Sep, 2022 - Comments: 0

A new research paper titled "FPGA Random Number Generator" was published by a researcher at Johns Hopkins University. According to the paper's abstract: "This paper offers a proof-of-concept for creating a verilog-based hardware design that utilizes random measurement and scrambling algorithms to generate 32-bit random synchronously with a single clock cycle on a field-programmable-gate-arr... » read more

Convolutional Neural Networks: Co-Design of Hardware Architecture and Compression Algorithm
By Technical Paper Link - 07 Sep, 2022 - Comments: 0

Researchers at Soongsil University (Korea) published "A Survey on Efficient Convolutional Neural Networks and Hardware Acceleration." Abstract: "Over the past decade, deep-learning-based representations have demonstrated remarkable performance in academia and industry. The learning capability of convolutional neural networks (CNNs) originates from a combination of various feature extraction... » read more

Evaluation of Automotive HW Trust Anchors Regarding Their Feasibility In Vehicle Architectures
By Technical Paper Link - 07 Sep, 2022 - Comments: 0

A new technical paper titled "Analysis and Evaluation of Hardware Trust Anchors in the Automotive Domain" was published by researchers at Fraunhofer Institute SIT and CARIAD. Abstract "Automotive architectures get increasingly more complex both regarding internal as well as external connections to offer new services like autonomous driving. This development further broadens the cyberattack ... » read more

Algorithm HW Framework That Minimizes Accuracy Degradation, Data Movement, And Energy Consumption Of DNN Accelerators (Georgia Tech)
By Technical Paper Link - 31 Aug, 2022 - Comments: 0

This new research paper titled "An Algorithm-Hardware Co-design Framework to Overcome Imperfections of Mixed-signal DNN Accelerators" was published by researchers at Georgia Tech. According to the paper's abstract, "In recent years, processing in memory (PIM) based mixed-signal designs have been proposed as energy- and area-efficient solutions with ultra high throughput to accelerate DNN com... » read more

Designing for FPGA Accelerators
By Technical Paper Link - 31 Aug, 2022 - Comments: 0

This research paper titled "High-Level Synthesis Hardware Design for FPGA-based Accelerators: Models, Methodologies, and Frameworks" was published by researchers at Università degli Studi di Trieste (Italy), Universidad Nacional de San Luis (Argentina), and the Abdus Salam International Centre for Theoretical Physics (Italy). According to the paper's abstract, "This paper presents a survey ... » read more

3D NAND: Scenarios For Scaling & Stacking
By Technical Paper Link - 25 Aug, 2022 - Comments: 0

A new research paper titled "Impact of Stacking-Up and Scaling-Down Bit Cells in 3D NAND on Their Threshold Voltages" was published by researchers at Sungkyunkwan University and Korea University. Abstract "Over the past few decades, NAND flash memory has advanced with exponentially-increasing bit growth. As bit cells in 3D NAND flash memory are stacked up and scaled down together, some pote... » read more

Finding the Scope of CXL-Enabled Tiered Memory System in Production
By Technical Paper Link - 25 Aug, 2022 - Comments: 0

This new technical paper titled "TPP: Transparent Page Placement for CXL-Enabled Tiered Memory" is presented by researchers at University of Michigan and Meta Inc. Abstract (partial) "We propose a novel OS-level application-transparent page placement mechanism (TPP) for efficient memory management. TPP employs a lightweight mechanism to identify and place hot and cold pages to appropriate... » read more

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