category: Design & Verification

category: IoT, Security & Automotive

Shallow Clock Tree Pre-Estimation for Designing Clock Tree Synthesizable Verilog RTLs (Kyungpook National University)
By Technical Paper Link - 31 Oct, 2023 - Comments: 0

A technical paper titled “Shallow Clock Tree Pre-Estimation for Designing Clock Tree Synthesizable Verilog RTLs” was published by researchers at Kyungpook National University. Abstract: "Clock tree synthesis (CTS) is an important process in determining overall chip timing and power consumption. The CTS is also a time-consuming process for checking the clock tree. If the chip design and sp... » read more

Analyzing The U.S. Advanced Packaging Ecosystem With Countermeasures To Mitigate HW Security Issues
By Technical Paper Link - 27 Oct, 2023 - Comments: 0

A technical paper titled “US Microelectronics Packaging Ecosystem: Challenges and Opportunities” was published by researchers at University of Florida, University of Miami, and Skywater Technology Foundry. Abstract: "The semiconductor industry is experiencing a significant shift from traditional methods of shrinking devices and reducing costs. Chip designers actively seek new technologica... » read more

Optimization Of The Interface Between The PD And The AFE In High-Speed, High-Density Optical Receivers
By Technical Paper Link - 27 Oct, 2023 - Comments: 0

A technical paper titled “Optimizing the Photodetector/Analog Front-End Interface in Optical Communication Receivers” was published by researchers at University of Toronto. Abstract: "This article addresses the optimization of the interface between the photodetector (PD) and the analog front-end in high-speed, high-density optical communication receivers. Specifically, the article focuses... » read more

LLMs For Hardware Design Verification
By Technical Paper Link - 16 Oct, 2023 - Comments: 0

A technical paper titled “LLM4DV: Using Large Language Models for Hardware Test Stimuli Generation” was published by researchers at University of Cambridge, lowRISC, and Imperial College London. Abstract: "Test stimuli generation has been a crucial but labor-intensive task in hardware design verification. In this paper, we revolutionize this process by harnessing the power of large langua... » read more

An Overview Of Current Projects In The Open Quantum Hardware Ecosystem With Recommendations 
By Technical Paper Link - 12 Oct, 2023 - Comments: 0

A technical paper titled “Open Hardware in Quantum Technology” was published by researchers at Unitary Fund, Qruise, Technical University of Valencia, M-Labs Limited, Lawrence Berkeley National Laboratory, Fermi National Accelerator Laboratory, Sandia National Laboratories, IQM Quantum Computers, PASQAL, Quantonation, Michigan State University, Università di Camerino, Microsoft Quantum, an... » read more

A Formal Verification Method To Detect Timing Side Channels In MCU SoCs
By Technical Paper Link - 11 Oct, 2023 - Comments: 0

A technical paper titled “A New Security Threat in MCUs – SoC-wide timing side channels and how to find them” was published by researchers at University of Kaiserslautern-Landau and Stanford University. Abstract: "Microarchitectural timing side channels have been thoroughly investigated as a security threat in hardware designs featuring shared buffers (e.g., caches) and/or parallelism b... » read more

Applying Machine Learning to EDA, FPGA Design Automation Tools
By Technical Paper Link - 11 Oct, 2023 - Comments: 0

A technical paper titled “Application of Machine Learning in FPGA EDA Tool Development” was published by researchers at the University of Texas Dallas. Abstract: "With the recent advances in hardware technologies like advanced CPUs and GPUs and the large availability of open-source libraries, machine learning has penetrated various domains, including Electronics Design Automation (EDA). E... » read more

LLM-Aided AI Accelerator Design Automation (Georgia Tech)
By Technical Paper Link - 28 Sep, 2023 - Comments: 0

A technical paper titled “GPT4AIGChip: Towards Next-Generation AI Accelerator Design Automation via Large Language Models” was published by researchers at Georgia Institute of Technology. Abstract: "The remarkable capabilities and intricate nature of Artificial Intelligence (AI) have dramatically escalated the imperative for specialized AI accelerators. Nonetheless, designing these accele... » read more

LLM-Assisted Generation Of Formal Verification Testbenches: RTL to SVA (Princeton)
By Technical Paper Link - 28 Sep, 2023 - Comments: 0

A technical paper titled “From RTL to SVA: LLM-assisted generation of Formal Verification Testbenches” was published by researchers at Princeton University. Abstract: "Formal property verification (FPV) has existed for decades and has been shown to be effective at finding intricate RTL bugs. However, formal properties, such as those written as System Verilog Assertions (SVA), are time-con... » read more

Improving ML-Based Device Modeling Using Variational Autoencoder Techniques
By Technical Paper Link - 27 Sep, 2023 - Comments: 0

A technical paper titled “Improving Semiconductor Device Modeling for Electronic Design Automation by Machine Learning Techniques” was published by researchers at Commonwealth Scientific and Industrial Research Organisation (CSIRO), Peking University, National University of Singapore, and University of New South Wales. Abstract: "The semiconductors industry benefits greatly from the integ... » read more

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