category: Design & Verification

category: IoT, Security & Automotive

New Architecture Elements For 5G RF Front-End Modules To Reduce Noise, Improve Efficiency, And Allow Multiple Radio Transmitters
By Technical Paper Link - 15 Aug, 2023 - Comments: 0

A technical paper titled “Circuits for 5G RF front-end modules” was published by researchers at Skyworks Solutions Inc. Abstract: "Worldwide adoption of fourth-generation wireless (4G) long-term evolution (LTE) smartphones and the actual transition to fifth-generation wireless (5G) is the main driving engine for semiconductor industry. 5G is expected to reach high data rate speeds (1 Gbps... » read more

A Search Framework That Optimizes Hybrid-Device IMC Architectures For DNNs, Using Chiplets
By Technical Paper Link - 08 Aug, 2023 - Comments: 0

A technical paper titled “HyDe: A Hybrid PCM/FeFET/SRAM Device-search for Optimizing Area and Energy-efficiencies in Analog IMC Platforms” was published by researchers at Yale University. Abstract: "Today, there are a plethora of In-Memory Computing (IMC) devices- SRAMs, PCMs & FeFETs, that emulate convolutions on crossbar-arrays with high throughput. Each IMC device offers its own pr... » read more

Modification Of An Existing E-Graph Based RTL Optimization Tool As A Formal Verification Assistant
By Technical Paper Link - 07 Aug, 2023 - Comments: 0

A technical paper titled “Datapath Verification via Word-Level E-Graph Rewriting” was published by researchers at Intel Corporation and Imperial College London. Abstract: "Formal verification of datapath circuits is challenging as they are subject to intense optimization effort in the design phase. Industrial vendors and design companies deploy equivalence checking against a golden or exi... » read more

A Chiplet-Based FHE Accelerator Design Enabling Scalability And Higher Throughput
By Technical Paper Link - 07 Aug, 2023 - Comments: 0

A technical paper titled “REED: Chiplet-Based Scalable Hardware Accelerator for Fully Homomorphic Encryption” was published by researchers at Graz University of Technology and Samsung Advanced Institute of Technology. Abstract: "Fully Homomorphic Encryption (FHE) has emerged as a promising technology for processing encrypted data without the need for decryption. Despite its potential, its... » read more

A Safety Island For Safe Use of HPC Devices For Safety-Critical Systems with RISC-V
By Technical Paper Link - 02 Aug, 2023 - Comments: 0

A technical paper titled “Envisioning a Safety Island to Enable HPC Devices in Safety-Critical Domains” was published by researchers at Barcelona Supercomputing Center and Intel. Abstract: "HPC (High Performance Computing) devices increasingly become the only alternative to deliver the performance needed in safety-critical autonomous systems (e.g., autonomous cars, unmanned planes) du... » read more

CNN Hardware Architecture With Weights Generator Module That Alleviates Impact Of The Memory Wall
By Technical Paper Link - 01 Aug, 2023 - Comments: 0

A technical paper titled “Mitigating Memory Wall Effects in CNN Engines with On-the-Fly Weights Generation” was published by researchers at Samsung AI Center and University of Cambridge. Abstract: "The unprecedented accuracy of convolutional neural networks (CNNs) across a broad range of AI tasks has led to their widespread deployment in mobile and embedded settings. In a pursuit for high... » read more

A Chiplet-Based Supercomputer For Generative LLMs That Optimizes Total Cost of Ownership
By Technical Paper Link - 20 Jul, 2023 - Comments: 0

A technical paper titled "Chiplet Cloud: Building AI Supercomputers for Serving Large Generative Language Models" was published by researchers at University of Washington and University of Sydney. Abstract: "Large language models (LLMs) such as ChatGPT have demonstrated unprecedented capabilities in multiple AI tasks. However, hardware inefficiencies have become a significant factor limiting ... » read more

Analog On-Chip Learning Circuits In Mixed-Signal Neuromorphic SNNs
By Technical Paper Link - 20 Jul, 2023 - Comments: 0

A technical paper titled "Neuromorphic analog circuits for robust on-chip always-on learning in spiking neural networks" was published by researchers at Institute of Neuroinformatics, University of Zurich, and ETH Zurich. Abstract: "Mixed-signal neuromorphic systems represent a promising solution for solving extreme-edge computing tasks without relying on external computing resources. Their s... » read more

System Level Power Integrity Verification For Multi-Core Microprocessors With FIVR
By Technical Paper Link - 15 Jul, 2023 - Comments: 0

A technical paper titled "A Compressed Multivariate Macromodeling Framework for Fast Transient Verification of System-Level Power Delivery Networks" was published by researchers at Politecnico di Torino and Intel Corporation. Abstract: This paper discusses a reduced-order modeling and simulation approach for fast transient power integrity verification at full system level. The reference str... » read more

Hardware-Efficient Approach To Defend Against Fault Attacks
By Technical Paper Link - 13 Jul, 2023 - Comments: 0

A technical paper titled "Fault Attacks on Access Control in Processors: Threat, Formal Analysis and Microarchitectural Mitigation" was published by researchers at University of Kaiserslautern-Landau. Abstract: "Process isolation is a key component of the security architecture in any hardware/software system. However, even when implemented correctly and comprehensively at the software (SW) le... » read more

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