category: Design & Verification

category: IoT, Security & Automotive

An Advanced Modeling Approach For Cyclic Safety Mechanisms In A Fault Tree Analysis
By Technical Paper Link - 08 Jul, 2023 - Comments: 0

A technical paper titled "Best Practices for Advanced Modeling of Safety Mechanisms in an FTA" was published by researchers at University of Stuttgart, Robert Bosch GmbH, Audi AG, and Porsche AG. Abstract: "To cope with the megatrends electrification, automated driving, and connectivity, new functionalities and electric and/or electronic systems must be developed, which require a safe power s... » read more

Heterogeneous Integration As A Path Towards Sustainable Computing, Using Chiplets
By Technical Paper Link - 06 Jul, 2023 - Comments: 0

A technical paper titled "Towards Sustainable Computing: Assessing the Carbon Footprint of Heterogeneous Systems" was published by researchers at Arizona State University and University of Minnesota. Abstract: "Decades of progress in energy-efficient and low-power design have successfully reduced the operational carbon footprint in the semiconductor industry. However, this has led to an incre... » read more

Self-Driving Cars: Formalization and Verification Of The Responsibility-Sensitive Safety (RSS) Model
By Technical Paper Link - 28 Jun, 2023 - Comments: 0

A technical paper titled “Slow Down, Move Over: A Case Study in Formal Verification, Refinement, and Testing of the Responsibility-Sensitive Safety Model for Self-Driving Cars” was published by researchers at Carnegie Mellon University. Abstract: "Technology advances give us the hope of driving without human error, reducing vehicle emissions and simplifying an everyday task with the futur... » read more

Leveraging Large Language Models (LLMs) To Perform SW-HW Co-Design
By Technical Paper Link - 28 Jun, 2023 - Comments: 0

A technical paper titled “On the Viability of using LLMs for SW/HW Co-Design: An Example in Designing CiM DNN Accelerators” was published by researchers at University of Notre Dame. Abstract: "Deep Neural Networks (DNNs) have demonstrated impressive performance across a wide range of tasks. However, deploying DNNs on edge devices poses significant challenges due to stringent power and com... » read more

The Implementation Of Cooperative Collision Avoidance For Connected Vehicles (Ohio State University)
By Technical Paper Link - 24 Jun, 2023 - Comments: 0

A technical paper titled “Cooperative Collision Avoidance in a Connected Vehicle Environment” was published by researchers at Ohio State University. Abstract: "Connected vehicle (CV) technology is among the most heavily researched areas in both the academia and industry. The vehicle to vehicle (V2V), vehicle to infrastructure (V2I) and vehicle to pedestrian (V2P) communication capabilitie... » read more

Fault Awareness And Reliability Improvements In a Fault-Tolerant RISC-V SoC (HARV-SoC)
By Technical Paper Link - 24 Jun, 2023 - Comments: 0

A technical paper titled “Enhancing Fault Awareness and Reliability of a Fault-Tolerant RISC-V System-on-Chip” was published by researchers at University of Montpellier and University of Vale do Itajaí. Abstract: "Recent research has shown interest in adopting the RISC-V processors for high-reliability electronics, such as aerospace applications. The openness of this architecture enables... » read more

Search Based Method For Identifying Aging Model Parameters
By Technical Paper Link - 24 Jun, 2023 - Comments: 0

A technical paper titled “Leveraging Public Information to Fit a Compact Hot Carrier Injection Model to a Target Technology” was published by researchers at University of Victoria. Abstract: "The design of countermeasures against integrated circuit counterfeit recycling requires the ability to simulate aging in CMOS devices. Electronic design automation tools commonly provide this ability... » read more

An Energy Efficient, Linux-Capable RISC-V Host Platform Designed For The Seamless Plug-In And Control Of Domain-Specific Accelerators
By Technical Paper Link - 14 Jun, 2023 - Comments: 0

A technical paper titled “Cheshire: A Lightweight, Linux-Capable RISC-V Host Platform for Domain-Specific Accelerator Plug-In” was published by researchers at ETH Zurich and University of Bologna. Abstract: "Power and cost constraints in the internet-of-things (IoT) extreme-edge and TinyML domains, coupled with increasing performance requirements, motivate a trend toward heterogeneous arc... » read more

Chiplets: Bridging The Gap Between The System Requirements And Design Aggregation, Planning, And Optimization
By Technical Paper Link - 14 Jun, 2023 - Comments: 0

A technical paper titled “System and Design Technology Co-optimization of Chiplet-based AI Accelerator with Machine Learning” was published by researchers at Auburn University. Abstract: "With the availability of advanced packaging technology and its attractive features, the chiplet-based architecture has gained traction among chip designers. The large design space and the lack of sys... » read more

Tools for Co-Designing HPC Systems Using RISC-V As A Demonstrator
By Technical Paper Link - 14 Jun, 2023 - Comments: 0

A technical paper titled “Software Development Vehicles to enable extended and early co-design: a RISC-V and HPC case of study” was published by researchers at Barcelona Supercomputing Center and FORTH. Abstract: "Prototyping HPC systems with low-to-mid technology readiness level (TRL) systems is critical for providing feedback to hardware designers, the system software team (e.g., co... » read more

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