Tools for Co-Designing HPC Systems Using RISC-V As A Demonstrator


A technical paper titled “Software Development Vehicles to enable extended and early co-design: a RISC-V and HPC case of study” was published by researchers at Barcelona Supercomputing Center and FORTH.


“Prototyping HPC systems with low-to-mid technology readiness level (TRL) systems is critical for providing feedback to hardware designers, the system software team (e.g., compiler developers), and early adopters from the scientific community. The typical approach to hardware design and HPC system prototyping often limits feedback or only allows it at a late stage. In this paper, we present a set of tools for co-designing HPC systems, called software development vehicles (SDV). We use an innovative RISC-V design as a demonstrator, which includes a scalar CPU and a vector processing unit capable of operating large vectors up to 16 kbits. We provide an incremental methodology and early tangible evidence of the co-design process that provide feedback to improve both architecture and system software at a very early stage of system development.”

Find the technical paper here. Published: June 2023 (preprint).

Mantovani, Filippo, Pablo Vizcaino, Fabio Banchelli, Marta Garcia-Gasulla, Roger Ferrer, Giorgos Ieronymakis, Nikos Dimou, Vassilis Papaefstathiou, and Jesus Labarta. “Software Development Vehicles to enable extended and early co-design: a RISC-V and HPC case of study.” arXiv preprint arXiv:2306.01797 (2023).

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