category: Manufacturing

category: IoT, Security & Automotive

EFO Errors In The Wire-Bonding Semiconductor Packaging Process
By Technical Paper Link - 19 Mar, 2025 - Comments: 0

A new technical paper titled "A Comparative Study on Various Au Wire Rinse Compositions and Their Effects on the Electronic Flame-Off Errors of Wire-Bonding Semiconductor Package" was published by researchers at Hanbat National University, Seoul National University and Chungnam National University. The paper states: "In this study, we identify the origin of electronic flame-off (EFO) erro... » read more

Energy-Efficient Scalable Silicon Photonic Platform For AI Accelerator HW
By Technical Paper Link - 12 Mar, 2025 - Comments: 0

A new technical paper titled "Large-Scale Integrated Photonic Device Platform for Energy-Efficient AI/ML Accelerators" was published by researchers at HP Labs, IIT Madras, Microsoft Research and University of Michigan. Abstract "The convergence of deep learning and Big Data has spurred significant interest in developing novel hardware that can run large artificial intelligence (AI) workload... » read more

Wafer-Level Test Infrastructure for Higher Parallel Wafer Level Testing of SoC
By Technical Paper Link - 03 Mar, 2025 - Comments: 0

A new technical paper titled "Design and Implementation of Test Infrastructure for Higher Parallel Wafer Level Testing of System-on-Chip" was published by researchers at Inha University and Teradyne. Abstract "Semiconductor companies have been striving to reduce their manufacturing costs. High parallelism is a key factor in reducing costs during wafer-level testing. Wafer testing is conduct... » read more

Synthesis Of An Ultrathin Vanadium Dioxide Film On A Flexible Substrate, Preserving Film’s Electrical Properties
By Technical Paper Link - 03 Mar, 2025 - Comments: 0

A new technical paper titled "Strain-free thin film growth of vanadium dioxide deposited on 2D atomic layered material of hexagonal boron nitride investigated by their thickness dependence of insulator–metal transition behavior" was published by researchers at Osaka University and National Institute for Materials Science. Abstract "We report on the preparation of vanadium dioxide (VO2) ul... » read more

3D Stacked Device Architecture Enabled By BEOL-Compatible Transistors (Stanford et al.)
By Technical Paper Link - 26 Feb, 2025 - Comments: 0

A new technical paper titled "Omni 3D: BEOL-Compatible 3-D Logic With Omnipresent Power, Signal, and Clock" was published by researchers at Stanford University, Intel Corporation and Carnegie Mellon University. Abstract "This article presents Omni 3D—a 3-D-stacked device architecture that is naturally enabled by back-end-of-line (BEOL)-compatible transistors. Omni 3D interleaves metal lay... » read more

Low-Temp Pressure-Assisted Liquid-Metal Printing for Oxide-TFTs
By Technical Paper Link - 25 Feb, 2025 - Comments: 0

A new technical paper titled "Low-temperature pressure-assisted liquid-metal printing for β-Ga2O3 thin-film transistors" was published by researchers at UCSD and National Tsing Hua University. Abstract "Developing a low-temperature and cost-effective manufacturing process for energy-efficient and high-performance oxide-thin-film transistors (TFTs) is a crucial step toward advanci... » read more

Low-Cost TSV Repair Architecture Specialized for Highly Clustered TSV Faults Within HBM
By Technical Paper Link - 20 Feb, 2025 - Comments: 0

A new technical paper titled "Low Cost TSV Repair Architecture Using Switch-Based Matrix for Highly Clustered Faults" was published by researchers at Yonsei University. Abstract "Through-silicon via (TSV), responsible for inter-layer communication in high-bandwidth memory (HBM), plays a critical role in HBM operation. Therefore, faults occur in TSVs can critically impact the entire chips. H... » read more

Material Properties of Si/SiGe Multi-layer Stacks For CFETs (Imec, Ghent U, et al.)
By Technical Paper Link - 19 Feb, 2025 - Comments: 0

A new technical paper titled "Epitaxial Si/SiGe Multi-Stacks: From Stacked Nano-Sheet to Fork-Sheet and CFET Devices" was published by researchers at Imec and Ghent University, et al. Abstract "After a short description of the evolution of metal-oxide-semiconductor device architectures and the corresponding requirements on epitaxial growth processes, the manuscript describes the material pr... » read more

CFETs with Optimized Buried Power Rails
By Technical Paper Link - 19 Feb, 2025 - Comments: 0

A technical paper titled "Buried power rail to suppress substrate leakage in complementary field effect transistor (CFET)" was published by researchers at Korea University and Sungkyunkwan University. Abstract "In the pursuit of minimizing the track height in standard cell, a design innovation incorporating complementary field-effect transistors (CFETs) and Buried Power Rail (BPR) technolog... » read more

Low-Temperature Solid-Liquid Interdiffusion Bonding For High-Density Interconnect Applications
By Technical Paper Link - 19 Feb, 2025 - Comments: 0

A new technical paper titled "Facilitating Small-Pitch Interconnects with Low-Temperature Solid-Liquid Interdiffusion Bonding" was published by researchers at Aalto University in Finland. Abstract "The trend for 3D heterogeneous integration drives the need for a low-temperature bonding process for high-density interconnects (HDI). The Cu-Sn-In based solid-liquid interdiffusion (SLID) is a p... » read more

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