Control of the Schottky barrier height in monolayer WS2 FETs using molecular doping (NIST)


A new research paper titled "Control of the Schottky barrier height in monolayer WS2 FETs using molecular doping" was published by researchers at NIST, Theiss Research, Naval Research Laboratory, and Nova Research. Abstract: "The development of processes to controllably dope two-dimensional semiconductors is critical to achieving next generation electronic and optoelectronic devices. Unde... » read more

Mass Production of Soft And Stretchable Electronics


This new technical paper titled "Scalable Manufacturing of Liquid Metal Circuits" was published by researchers at Carnegie Mellon University. The work presents "a novel technique for scalable and reproducible manufacturing of LM-based SSEs [soft and stretchable electronics] with integrated solid-state microelectronic components. The manufacturing technique is based on a selective metal-alloy... » read more

Mass Producing Qubits (Imec and KU Leuven)


This new technical paper titled "Path toward manufacturable superconducting qubits with relaxation times exceeding 0.1 ms" was published by researchers at Imec and KU Leuven. Abstract "As the superconducting qubit platform matures towards ever-larger scales in the race towards a practical quantum computer, limitations due to qubit inhomogeneity through lack of process control become app... » read more

Particle Removal From EUV Photomasks


This technical paper titled "AFM-Based Hamaker Constant Determination with Blind Tip Reconstruction" was just published by researchers at ASML, RWTH Aachen University, and AMO GmbH. The research reports a vaccuum AFM-based approach for particle removal from EUV photomasks. Find the technical paper here. Published August 2022. Ku, B., van de Wetering, F., Bolten, J., Stel, B., van de K... » read more

ML Architecture for Solving the Inverse Problem for Matter Wave Lithography: LACENET


This recent technical paper titled "Realistic mask generation for matter-wave lithography via machine learning" was published by researchers at University of Bergen (Norway). Abstract: "Fast production of large area patterns with nanometre resolution is crucial for the established semiconductor industry and for enabling industrial-scale production of next-generation quantum devices. Metasta... » read more

Novel In-Pixel-in-Memory (P2M) Paradigm for Edge Intelligence (USC)


A new technical paper titled "A processing-in-pixel-in-memory paradigm for resource-constrained TinyML applications" was published by researchers at University of Southern California (USC). According to the paper, "we propose a novel Processing-in-Pixel-in-memory (P2M) paradigm, that customizes the pixel array by adding support for analog multi-channel, multi-bit convolution, batch normaliza... » read more

Effects of Size Scaling and Device Architecture on the Radiation Response of Nanoscale MOS Transistors


A new technical paper titled "Perspective on radiation effects in nanoscale metal–oxide–semiconductor devices" was published by a researcher at Vanderbilt University, Nashville, Tennessee. The work was partially supported by the Defense Threat Reduction Agency and by the U.S. Air Force Office of Scientific Research and Air Force Research Laboratory. According to the paper, "this Perspect... » read more

State Of The Art And Recent Progress of Reconfigurable Electronic Devices Based on 2D Materials


A new technical paper titled "Emerging reconfigurable electronic devices based on two-dimensional materials: A review" was just published by researchers at TU Dresden, NaMLAb gGmbH, and RWTH Aachen University. Abstract "As the dimensions of the transistor, the key element of silicon technology, are approaching their physical limits, developing semiconductor technology with novel concepts an... » read more

Beyond 5nm: Review of Buried Power Rails & Back-Side Power


A new technical paper titled "A Holistic Evaluation of Buried Power Rails and Back-Side Power for Sub-5 nm Technology Nodes" is presented by researchers at UT Austin, Arm Research, and imec. Find the technical paper here. Published July 2022. S. S. T. Nibhanupudi et al., "A Holistic Evaluation of Buried Power Rails and Back-Side Power for Sub-5 nm Technology Nodes," in IEEE Transactions... » read more

Reporting and Benchmarking Process For A 2D Semiconductor FET


New research paper titled "How to Report and Benchmark Emerging Field-Effect Transistors" was published from researchers at NIST, Purdue University, UCLA, Theiss Research, Peking University, NYU, Imec, RWTH Aachen, and others. "Emerging low-dimensional nanomaterials have been studied for decades in device applications as field-effect transistors (FETs). However, properly reporting and compar... » read more

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