category: Manufacturing

category: IoT, Security & Automotive

The Decadal Plan for Semiconductors
By Technical Paper Link - 08 Feb, 2021 - Comments: 0

Semiconductor Research Corporation and Semiconductor Industry Association released the full Decadal Plan for Semiconductors: a roadmap, for 2030 and beyond. It’s a report that outlines chip research and funding priorities for the next decade. Find the Report Overview, Abridged Report and the Full Report here. » read more

Pressure-induced Anderson-Mott transition in elemental tellurium
By Technical Paper Link - 07 Jan, 2021 - Comments: 0

Oliveira, J.F., Fontes, M.B., Moutinho, M. et al. Pressure-induced Anderson-Mott transition in elemental tellurium. Commun Mater 2, 1 (2021). https://doi.org/10.1038/s43246-020-00110-1 Abstract: "Elemental tellurium is a small band-gap semiconductor, which is always p-doped due to the natural occurrence of vacancies. Its chiral non-centrosymmetric structure, characterized by helical chains ... » read more

Improving EUV Underlayer Coating Defectivity Using Point-Of-Use Filtration
By Brewer Science - 18 Nov, 2020 - Comments: 0

Authors: Aiwen Wu (Entegris, Inc. — United States), Hareen Bayana (Entegris GmbH — Germany), Philippe Foubert (imec — Belgium), Andrea Chacko and Douglas Guererro (Brewer Science, Inc. — United States). This paper describes efforts to leverage different filtration parameters, including retention ratings and membrane materials, to understand their impact on EUV underlayer coating defe... » read more

Graphene and two-dimensional materials for silicon technology
By Technical Paper Link - 02 Oct, 2020 - Comments: 1

Abstract: "The development of silicon semiconductor technology has produced breakthroughs in electronics—from the microprocessor in the late 1960s to early 1970s, to automation, computers and smartphones—by downscaling the physical size of devices and wires to the nanometre regime. Now, graphene and related two-dimensional (2D) materials offer prospects of unprecedented advances in device ... » read more

Development Of Planarizing Spin-On Carbon Materials For High-Temperature Processes
By Brewer Science - 20 Aug, 2020 - Comments: 0

Multilayer lithography is used for advanced semiconductor processes to pattern complex structures. As more and more procedures incorporate a high-temperature process, such as chemical vapor deposition (CVD), the need for thermally stable materials increases. For certain applications, a spin-on carbon (SOC) layer under the CVD layer is required to survive through a high-temperature process. ... » read more

Super Planarizing Material For Trench And Via Arrays
By Brewer Science - 21 May, 2020 - Comments: 0

As device design scales and becomes more complex, fine control of patterning and transfer steps is integral. Planarization of deep trenches and via arrays has always been a challenge. Aspect ratios continue to increase while critical dimensions shrink, and typical trench fill schemes are no longer able to meet the fill and planarization requirements. Traditional design of spin-on carbon (SOC) m... » read more

Thin Film Characterization For Advanced Patterning
By Brewer Science - 18 Mar, 2020 - Comments: 0

Authors: Zhimin Zhu; Xianggui Ye; Sean Simmons; Catherine Frank; Tim Limmer; James Lamb Brewer Science, Inc. (United States) A variable-angle spectroscopic ellipsometer (VASE) is an essential tool for measuring the thickness of a thin film, as well as its n and k optical parameters. However, for films thinner than 10 nm, precise measurement is very challenging. In this paper, the root cause... » read more

Design Comparison of SiC MOSFETs for Linear-Mode Operation
By Technical Paper Link - 02 Oct, 2019 - Comments: 0

Source: US Army Research Lab Authors: Heather O'Brien, Damian Urciuoli, Aderinto Ogunniyi, Brett Hull August 2019 "Abstract: Silicon carbide metal-oxide semiconductor field-effect transistors (MOSFETs) were designed and fabricated for linear-mode applications. The MOSFETs have a chip area of 3.3 ? 3.3 mm and a voltage-blocking rating up to 1200 V. The device design parameters, such as chan... » read more

Investigation and Methods Using Various Release and Thermoplastic Bonding Materials to Reduce Die Shift and Wafer Warpage for eWLB Chip-First Processes
By Brewer Science - 14 Aug, 2019 - Comments: 0

Today's fan-out wafer-level packaging (FOWLP) processes use organic substrates composed of epoxy mold compound (EMC) created using a thermal compression process. EMC wafers are a cost-effective way to achieve lower profile packages without using an inorganic substrate to produce chip packages that are thinner and faster without the need for interposers or through-silicon-vias (TSVs). One approa... » read more

Sacrificial Laser Release Materials For RDL-First Fan-Out Packaging
By Brewer Science - 11 Jun, 2018 - Comments: 0

The semiconductor industry is in a new age where device scaling will not continue to provide the cost reductions or performance improvements at a similar rate to past years when Moore’s law was the guiding principle for IC scaling. The cost of scaling below 7 nm nodes is rising substantially and requires significant investment in capital equipment and R&D spending for next-generation lithogra... » read more

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