Demonstrating A 2D–0D Hybrid Optical Multi-Level Memory Device Operated By Laser Pulses


A technical paper titled “Probing Optical Multi-Level Memory Effects in Single Core–Shell Quantum Dots and Application Through 2D-0D Hybrid Inverters” was published by researchers at Korea Institute of Science and Technology (KIST), Korea University, Daegu Gyeongbuk Institute of Science and Technology (DGIST), National Institute for Materials Science (Japan), and University of Science and... » read more

Efficient LLM Inference With Limited Memory (Apple)


A technical paper titled “LLM in a flash: Efficient Large Language Model Inference with Limited Memory” was published by researchers at Apple. Abstract: "Large language models (LLMs) are central to modern natural language processing, delivering exceptional performance in various tasks. However, their intensive computational and memory requirements present challenges, especially for device... » read more

Large-Scale Integration Of 2D Materials As The Semiconducting Channel In An In-Memory Processor (EPFL)


A technical paper titled “A large-scale integrated vector-matrix multiplication processor based on monolayer molybdenum disulfide memories” was published by researchers at École Polytechnique Fédérale de Lausanne (EPFL). Abstract: "Data-driven algorithms—such as signal processing and artificial neural networks—are required to process and extract meaningful information from the mass... » read more

Mixed SRAM And eDRAM Cell For Area And Energy-Efficient On-Chip AI Memory (Yale Univ.)


A new technical paper titled "MCAIMem: a Mixed SRAM and eDRAM Cell for Area and Energy-efficient on-chip AI Memory" was published by researchers at Yale University. Abstract: "AI chips commonly employ SRAM memory as buffers for their reliability and speed, which contribute to high performance. However, SRAM is expensive and demands significant area and energy consumption. Previous studies... » read more

Analog Planar Memristor Device: Developing, Designing, and Manufacturing


A new technical paper titled "Analog monolayer SWCNTs-based memristive 2D structure for energy-efficient deep learning in spiking neural networks" was published by researchers at Delft University of Technology and Khalifa University. Abstract: "Advances in materials science and memory devices work in tandem for the evolution of Artificial Intelligence systems. Energy-efficient computation... » read more

Memory Devices-Based Bayesian Neural Networks For Edge AI


A new technical paper titled "Bringing uncertainty quantification to the extreme-edge with memristor-based Bayesian neural networks" was published by researchers at Université Grenoble Alpes, CEA, LETI, and CNRS. Abstract: "Safety-critical sensory applications, like medical diagnosis, demand accurate decisions from limited, noisy data. Bayesian neural networks excel at such tasks, offering... » read more

FeFET Memory Encrypted Inside The Storage Array


A new technical paper titled "Embedding security into ferroelectric FET array via in situ memory operation" was published by researchers at Pennsylvania State University, University of Notre Dame, Fraunhofer IPMS, National University of Singapore, and North Dakota State University. Abstract "Non-volatile memories (NVMs) have the potential to reshape next-generation memory systems because of... » read more

Enabling Scalable Accelerator Design On Distributed HBM-FPGAs (UCLA)


A technical paper titled “TAPA-CS: Enabling Scalable Accelerator Design on Distributed HBM-FPGAs” was published by researchers at University of California Los Angeles. Abstract: "Despite the increasing adoption of Field-Programmable Gate Arrays (FPGAs) in compute clouds, there remains a significant gap in programming tools and abstractions which can leverage network-connected, cloud-scale... » read more

Alleviating the DRAM Capacity Bottleneck in Consumer Devices with NVMs


A new technical paper titled "Extending Memory Capacity in Modern Consumer Systems With Emerging Non-Volatile Memory: Experimental Analysis and Characterization Using the Intel Optane SSD" was published by researchers at ETH Zurich, University of Illinois Urbana-Champaign, Google, and Rivos. Abstract Excerpt "DRAM scalability is becoming a limiting factor to the available memory capacity in... » read more

Neuromorphic Devices Based On Memristive Nanowire Networks


A technical paper titled “Online dynamical learning and sequence memory with neuromorphic nanowire networks” was published by researchers at University of Sydney, University of California Los Angeles (UCLA), National Institute for Materials Science (NIMS), Kyushu Institute of Technology (Kyutech), and University of Sydney Nano Institute. Abstract: "Nanowire Networks (NWNs) belong to an em... » read more

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