category: Memory

category: IoT, Security & Automotive

Redesigning Core and Cache Hierarchy For A General-Purpose Monolithic 3D System
By Technical Paper Link - 24 Oct, 2022 - Comments: 0

A technical paper titled "RevaMp3D: Architecting the Processor Core and Cache Hierarchy for Systems with Monolithically-Integrated Logic and Memory" was published by researchers at ETH Zürich, KMUTNB, NTUA, and University of Toronto. Abstract: "Recent nano-technological advances enable the Monolithic 3D (M3D) integration of multiple memory and logic layers in a single chip with fine-graine... » read more

Memory-Computation Decoupling Execution To Achieve Ideal All-Bank PIM Performance
By Technical Paper Link - 18 Oct, 2022 - Comments: 0

A new technical paper titled "Achieving the Performance of All-Bank In-DRAM PIM With Standard Memory Interface: Memory-Computation Decoupling" was published by researchers at Korea University. "This paper proposed the memory-computation decoupled PIM architecture to provide the performance comparable to the all-bank PIM while preserving the standard DRAM interface, i.e., DRAM commands, powe... » read more

Nonvolatile ECRAM With A Short-Circuit Retention Time Several Orders of Magnitude Higher Than Previously Shown
By Technical Paper Link - 18 Oct, 2022 - Comments: 0

A new technical paper titled "Nonvolatile Electrochemical Random-Access Memory Under Short Circuit" was published by researchers at University of Michigan and Sandia National Laboratories. Abstract "Electrochemical random-access memory (ECRAM) is a recently developed and highly promising analog resistive memory element for in-memory computing. One longstanding challenge of ECRAM is attainin... » read more

A Full-Stack Domain-Specific Overlay Generation Framework Verified On FPGA
By Technical Paper Link - 12 Oct, 2022 - Comments: 0

A new technical paper titled "OverGen: Improving FPGA Usability through Domain-specific Overlay Generation" by researchers at UCLA and Chinese Academy of Sciences. "Our essential idea is to develop a hardware generation framework targeting a highly-customizable overlay, so that the abstraction gap can be lowered by tuning the design instance to applications of interest. We leverage and ext... » read more

Training a ML model On An Intelligent Edge Device Using Less Than 256KB Memory
By Technical Paper Link - 11 Oct, 2022 - Comments: 0

A new technical paper titled "On-Device Training Under 256KB Memory" was published by researchers at MIT and MIT-IBM Watson AI Lab. “Our study enables IoT devices to not only perform inference but also continuously update the AI models to newly collected data, paving the way for lifelong on-device learning. The low resource utilization makes deep learning more accessible and can have a bro... » read more

Adaptive Memristive Hardware
By Technical Paper Link - 02 Oct, 2022 - Comments: 0

A new technical paper titled "Self-organization of an inhomogeneous memristive hardware for sequence learning" was just published by researchers at University of Zurich, ETH Zurich, Université Grenoble Alpes, CEA, Leti and Toshiba. "We design and experimentally demonstrate an adaptive hardware architecture Memristive Self-organizing Spiking Recurrent Neural Network (MEMSORN). MEMSORN incorp... » read more

Framework Based on an RISC-V Microprocessor Supporting LiM Operations
By Technical Paper Link - 29 Sep, 2022 - Comments: 0

A new technical paper titled "RISC-Vlim, a RISC-V Framework for Logic-in-Memory Architectures" was published by researchers at Politecnico di Torino (Italy), Univerity of Tor Vergata (Italy), and University of Twente (The Netherlands). Abstract: "Most modern CPU architectures are based on the von Neumann principle, where memory and processing units are separate entities. Although processin... » read more

Decreasing Refresh Latency of Off-the-Shelf DRAM Chips
By Technical Paper Link - 28 Sep, 2022 - Comments: 0

A new technical paper titled "HiRA: Hidden Row Activation for Reducing Refresh Latency of Off-the-Shelf DRAM Chips" was published by researchers at ETH Zürich, TOBB University of Economics and Technology and Galicia Supercomputing Center (CESGA). Abstract "DRAM is the building block of modern main memory systems. DRAM cells must be periodically refreshed to prevent data loss. Refresh oper... » read more

Setting The Memory Controller Free From Managing DRAM Maintenance Ops (ETH Zurich)
By Technical Paper Link - 14 Sep, 2022 - Comments: 0

A new technical paper titled "A Case for Self-Managing DRAM Chips: Improving Performance, Efficiency, Reliability, and Security via Autonomous in-DRAM Maintenance Operations" was published by researchers at ETH Zurich. Abstract: "The rigid interface of current DRAM chips places the memory controller completely in charge of DRAM control. Even DRAM maintenance operations, which are used to en... » read more

Radiation-Hardened Non-Volatile Magnetic Latch That Tolerates SNUs and DNUs
By Technical Paper Link - 13 Sep, 2022 - Comments: 0

A research paper titled "A Radiation-Hardened Non-Volatile Magnetic Latch with High Reliability and Persistent Storage" was published by researchers at Anhui University, Hefei University of Technology, LIRMM, and Kyutech. According to the abstract: "Based on an advanced triple-path dual-interlocked-storage-cell (TPDICE) and MTJs, this paper proposes a radiation-hardened non-volatile magneti... » read more

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