category: Memory

category: IoT, Security & Automotive

Investigation Of Self-Heating Effects on Fe-FinFETs On IMC Applications (TU Munich, IIT, U. Stuttgart)
By Technical Paper Link - 04 May, 2025 - Comments: 0

A new technical paper titled "Investigating Self-Heating Effects in Ferroelectric FinFETs for Reliable In-Memory Computing" was published by researchers at TU Munich, University of Stuttgart and Indian Institute of Technology, Kanpur. Abstract "Ferroelectric (Fe) FET has emerged as a promising candidate for efficient in-memory computing due to its properties, such as non-volatility and lo... » read more

Optimizing End-to-End Communication And Workload Partitioning In MCM Accelerators (Georgia Tech)
By Technical Paper Link - 03 May, 2025 - Comments: 0

A new technical paper titled "MCMComm: Hardware-Software Co-Optimization for End-to-End Communication in Multi-Chip-Modules" was published by researchers at Georgia Tech. Abstract "Increasing AI computing demands and slowing transistor scaling have led to the advent of Multi-Chip-Module (MCMs) based accelerators. MCMs enable cost-effective scalability, higher yield, and modular reuse by par... » read more

Controlled Shared Memory For Dynamically Controlling Data Communication Via Shared Memory Approaches (ASU, Intel)
By Technical Paper Link - 27 Apr, 2025 - Comments: 0

A new technical paper titled "Controlled Shared Memory (COSM) Isolation: Design and Testbed Evaluation" was published by researchers at Arizona State University and Intel Corporation. Abstract "Recent memory sharing approaches, e.g., based on the Compute Express Link (CXL) standard, allow the flexible high-speed sharing of data (i.e., data communication) among multiple hosts. In information... » read more

Impact Of Cryogenic Temps On The Minimum-Operating Voltage Of 5nm FinFETs-Based SRAM (IIT, UC Berkeley et al)
By Technical Paper Link - 25 Apr, 2025 - Comments: 0

A new technical paper titled "An Investigation of Minimum Supply Voltage of 5nm SRAM from 300K down to 10K" was published by researchers at Indian Institute of Technology, UC Berkeley and Munich Institute of Robotics and Machine Intelligence. Abstract "In this article, we present a comprehensive study of the impact of cryogenic temperatures on the minimum-operating voltage (Vmin) of 5 nm ... » read more

HW-based Heterogeneous Memory Management for LLM Inferencing (KAIST, Stanford Unversity)
By Technical Paper Link - 22 Apr, 2025 - Comments: 0

A new technical paper titled "Hardware-based Heterogeneous Memory Management for Large Language Model Inference" was published by researchers at KAIST and Stanford University. Abstract "A large language model (LLM) is one of the most important emerging machine learning applications nowadays. However, due to its huge model size and runtime increase of the memory footprint, LLM inferences suf... » read more

Single Transistor Memory Cell C2RAM Based On FDSOI For Quantum And Neuromorphic
By Technical Paper Link - 15 Apr, 2025 - Comments: 0

A new technical paper titled "An Energy Efficient Memory Cell for Quantum and Neuromorphic Computing at Low Temperatures" was published by researchers at Forschungszentrum Jülich, RWTH Aachen University and SOITEC. Abstract: "Efficient computing in cryogenic environments, including classical von Neumann, quantum, and neuromorphic systems, is poised to transform big data processing. The que... » read more

ReRAM-Based, In-Memory Implementation Of Stochastic Computing
By Technical Paper Link - 14 Apr, 2025 - Comments: 0

A new technical paper titled "All-in-Memory Stochastic Computing using ReRAM" was published by researchers at TU Dresden, Center for Scalable Data Analytics and Artificial Intelligence (ScaDS.AI), Case Western Reserve University, University of Louisiana at Lafayette and Barkhausen Institut. Abstract "As the demand for efficient, low-power computing in embedded and edge devices grows, tradit... » read more

Side-by-Side Benchmark of NPU Platforms (Imperial College London, Cambridge)
By Technical Paper Link - 05 Apr, 2025 - Comments: 0

A new technical paper titled "Benchmarking Ultra-Low-Power μNPUs" was published by researchers at Imperial College London and University of Cambridge. Abstract "Efficient on-device neural network (NN) inference has various advantages over cloud-based processing, including predictable latency, enhanced privacy, greater reliability, and reduced operating costs for vendors. This has sparked t... » read more

Photonic-SRAM Bitcell for High-Speed On-Chip Photonic Memory and Compute Systems (UW, USC, GF)
By Technical Paper Link - 04 Apr, 2025 - Comments: 0

A new technical paper titled "Design of Energy-Efficient Cross-coupled Differential Photonic-SRAM (pSRAM) Bitcell for High-Speed On-Chip Photonic Memory and Compute Systems" was published by researchers at University of Wisconsin–Madison, USC and GlobalFoundries. Abstract "In this work, we propose a novel differential photonic static random access memory (pSRAM) bitcell design using fabri... » read more

Adaptive RISC-V Cache Architecture for Near-Memory Extensions (Politecnico di Torino, EPFL)
By Technical Paper Link - 04 Apr, 2025 - Comments: 0

A new technical paper titled "ARCANE: Adaptive RISC-V Cache Architecture for Near-memory Extensions" was published by researchers at Politecnico di Torino and EPFL. Abstract "Modern data-driven applications expose limitations of von Neumann architectures - extensive data movement, low throughput, and poor energy efficiency. Accelerators improve performance but lack flexibility and require... » read more

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