category: Memory

category: IoT, Security & Automotive

Neuromorphic electronics based on copying and pasting the brain
By Technical Paper Link - 09 Nov, 2021 - Comments: 1

Abstract: "Reverse engineering the brain by mimicking the structure and function of neuronal networks on a silicon integrated circuit was the original goal of neuromorphic engineering, but remains a distant prospect. The focus of neuromorphic engineering has thus been relaxed from rigorous brain mimicry to designs inspired by qualitative features of the brain, including event-driven sign... » read more

Standards for the Characterization of Endurance in Resistive Switching Devices
By Technical Paper Link - 03 Nov, 2021 - Comments: 0

Abstract "Resistive switching (RS) devices are emerging electronic components that could have applications in multiple types of integrated circuits, including electronic memories, true random number generators, radiofrequency switches, neuromorphic vision sensors, and artificial neural networks. The main factor hindering the massive employment of RS devices in commercial circuits is related to... » read more

Nanoporous Dielectric Resistive Memories Using Sequential Infiltration Synthesis
By Technical Paper Link - 06 Oct, 2021 - Comments: 0

Abstract "Resistance switching in metal–insulator–metal structures has been extensively studied in recent years for use as synaptic elements for neuromorphic computing and as nonvolatile memory elements. However, high switching power requirements, device variabilities, and considerable trade-offs between low operating voltages, high on/off ratios, and low leakage have limited their utility... » read more

Modeling electrical conduction in resistive-switching memory through machine learning
By Technical Paper Link - 04 Oct, 2021 - Comments: 0

Published in AIP Advances on July 13, 2021. Read the full paper (open access). Abstract Traditional physical-based models have generally been used to model the resistive-switching behavior of resistive-switching memory (RSM). Recently, vacancy-based conduction-filament (CF) growth models have been used to model device characteristics of a wide range of RSM devices. However, few have focused o... » read more

SMASH: Synchronized Many-sided Rowhammer Attacks from JavaScript
By Technical Paper Link - 08 Sep, 2021 - Comments: 0

Authors: Finn de Ridder, ETH Zurich and VU Amsterdam; Pietro Frigo, Emanuele Vannacci, Herbert Bos, and Cristiano Giuffrida, VU Amsterdam; Kaveh Razavi, ETH Zurich Abstract: "Despite their in-DRAM Target Row Refresh (TRR) mitigations, some of the most recent DDR4 modules are still vulnerable to many-sided Rowhammer bit flips. While these bit flips are exploitable from native code, tri... » read more

Memory Technology: Innovations needed for continued technology scaling and enabling advanced computing systems
By Technical Paper Link - 03 Sep, 2021 - Comments: 0

Abstract: "An increasing demand for data generation, storage, and intelligence generation from data is driving advances in memory technology and advanced computing applications. Memory performance is starting to define modern day computing in both mobile and server environments. There is an absolute need to continue the tremendous pace of memory technology improvements to deliver performanc... » read more

Dynamic Flash Memory with Dual Gate Surrounding Gate Transistor (SGT)
By Technical Paper Link - 03 Sep, 2021 - Comments: 0

Abstract: "This paper proposes an ultra-scaled memory device, called `Dynamic Flash Memory (DFM)'. With a dual-gate Surrounding Gate Transistor (SGT), a capacitorless 4F2 cell can be achieved. Similar to DRAM [1], refresh is needed, but high speed block refresh can improve the duty ratio. Analogous to Flash [2], three fundamental operations of “0” Erase, “1” Program, and Read are nee... » read more

Convolutional Compaction-Based MRAM Fault Diagnosis
By Technical Paper Link - 03 Sep, 2021 - Comments: 0

Abstract: "Spin-transfer torque magnetoresistive random-access memories (STT-MRAMs) are gradually superseding conventional SRAMs as last-level cache in System-on-Chip designs. Their manufacturing process includes trimming a reference resistance in STT-MRAM modules to reliably determine the logic values of 0 and 1 during read operations. Typically, an on-chip trimming routine consists of mult... » read more

MBIST-supported Trim Adjustment to Compensate Thermal Behavior of MRAM
By Technical Paper Link - 03 Sep, 2021 - Comments: 0

Abstract: "Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) is one of the most promising candidates to replace conventional embedded memory such as Static RAM and Dynamic RAM. However, due to the small on/off ratio of MRAM cells, process variations may reduce the operating margin of a chip. Reference trimming was suggested as one of the ways to reduce variation impact to the chi... » read more

Intermittent Undefined State Fault in RRAMs
By Technical Paper Link - 03 Sep, 2021 - Comments: 1

Abstract: " Industry is prototyping and commercializing Resistive Random Access Memories (RRAMs). Unfortunately, RRAM devices introduce new defects and faults. Hence, high-quality test solutions are urgently needed. Based on silicon measurements, this paper identifies a new RRAM unique fault, the Intermittent Undefined State Fault (IUSF); this fault causes the RRAM device to intermittently c... » read more

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