Holistic Die-to-Die Interface Design Methodology for 2.5-D Multichip-Module Systems


Abstract: "More than Moore technologies can be supported by system-level diversification enabled by chiplet-based integrated systems within multichip modules (MCMs) and silicon interposer-based 2.5-D systems. The division of large system-on-chip dies into smaller chiplets with different technology nodes specific to the chiplet application requirement enables the performance enhancement at the ... » read more

Research on the Humidity Resistance Reliability of Different Packaging Structures


Abstract "Packaging process is an indispensable part in the process of electronic components manufacturing, and its packaging quality directly affects the nominal power, reliability and other functions of the product in the subsequent application process. Through the research on the humidity resistance reliability of different packaging structures, C-Mount packaging structure, TO packaging str... » read more

A review of interconnect materials used in emerging memory device packaging: first- and second-level interconnect materials


Abstract "The main motivation of this review is to study the evolution of first and second level of interconnect materials used in memory device semiconductor packaging. Evolutions of bonding wires from gold (Au) to silver (Ag) or copper (Cu) have been reported and studied in previous literatures for low-cost solution, but Au wire still gives highest rating in terms of the performance of tempe... » read more

Research on Wire Sweep of Integrated Circuit Packaging Based on Three-dimensional Flow Simulation


Abstract: "Semiconductor manufacturing technology is becoming more and more rapidly. In the process of Integrated Circuit (IC) encapsulation, when wires contact each other, it will cause short circuit. Wire sweep has become the main factor affecting the reliability of the product. Therefore, it is a great challenge to master wire sweep in IC packaging process. This paper takes Low Profile Fi... » read more

Chiplet-Based Advanced Packaging Technology from 3D/TSV to FOWLP/FHE


T. Fukushima, "Chiplet-Based Advanced Packaging Technology from 3D/TSV to FOWLP/FHE," 2021 Symposium on VLSI Circuits, 2021, pp. 1-2, doi: 10.23919/VLSICircuits52068.2021.9492335. Abstract: "More recently, "chiplets" are expected for further scaling the performance of LSI systems. However, system integration with the chiplets is not a new methodology. The basic concept dates back well over ... » read more

Wafer-Level Fan-Out For High-Performance, Low-Cost Packaging Of Monolithic RF MEMS/CMOS


Navigating the trade-offs between performance, size, cost and reliability can be a challenge when considering integrated circuit (IC) packaging and the end-application. The integration of micro-electromechanical systems (MEMS), either monolithic or heterogeneous, introduces yet another level of complexity that has only recently been a major focus of multi-device packaging [1]. Wafer-level fanou... » read more

Extremely Large Exposure Field w/Fine Resolution Lithography Tech To Enable Next-Gen Panel Level Advanced Packaging


Abstract—"The growing demand for heterogeneous integration is driven by the 5G market that includes smartphones, data centers, servers, HPC, AI and IoT applications. Next-generation packaging technologies require tighter overlay to accommodate a larger package size with finer pitch chip interconnects on large format flexible panels. Heterogeneous integration enables next-generation device per... » read more

Recent Advances in Thermal Metamaterials and Their Future Applications for Electronics Packaging


Abstract: "Thermal metamaterials exhibit thermal properties that do not exist in nature but can be rationally designed to offer unique capabilities of controlling heat transfer. Recent advances have demonstrated successful manipulation of conductive heat transfer and led to novel heat guiding structures such as thermal cloaks, concentrators, etc. These advances imply new opportunities to gui... » read more

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