Heterogeneous Integration As A Path Towards Sustainable Computing, Using Chiplets


A technical paper titled "Towards Sustainable Computing: Assessing the Carbon Footprint of Heterogeneous Systems" was published by researchers at Arizona State University and University of Minnesota. Abstract: "Decades of progress in energy-efficient and low-power design have successfully reduced the operational carbon footprint in the semiconductor industry. However, this has led to an incre... » read more

Impact of CMOS Image Sensors Fabrication Processes On The Quality Of Smartphone Pictures


A technical paper titled “A Review of the Recent Developments in the Fabrication Processes of CMOS Image Sensors for Smartphones” was published by researchers at Texas A&M University. Abstract: "CMOS Image Sensors are experiencing significant growth due to their capabilities to be integrated in smartphones with refined image quality. One of the major contributions to the growth of ima... » read more

Chiplets: Bridging The Gap Between The System Requirements And Design Aggregation, Planning, And Optimization


A technical paper titled “System and Design Technology Co-optimization of Chiplet-based AI Accelerator with Machine Learning” was published by researchers at Auburn University. Abstract: "With the availability of advanced packaging technology and its attractive features, the chiplet-based architecture has gained traction among chip designers. The large design space and the lack of sys... » read more

Framework To Compile Quantum Programs Onto Chiplets (UCSB, Cisco)


A technical paper titled "Compilation for Quantum Computing on Chiplets" was published by researchers at UC Santa Barbara and Cisco Quantum Lab. Abstract: "Chiplet architecture is an emerging architecture for quantum computing that could significantly increase qubit resources with its great scalability and modularity. However, as the computing scale increases, communication between qubits w... » read more

NIST Releases “Vision And Strategy for the National Semiconductor Technology Center”


A paper titled "A Vision and Strategy for the National Semiconductor Technology Center" was published by the U.S. Department of Commerce’s National Institute of Standards and Technology (NIST). The paper describes how the NSTC (National Semiconductor Technology Center) will develop and safeguard chips and technologies of the future. “The NSTC will be an ambitious public-private consortiu... » read more

Data-Centric Reconfigurable Array Chiplets (Princeton)


A technical paper titled "Massive Data-Centric Parallelism in the Chiplet Era" was published by researchers at Princeton University. Abstract: "Traditionally, massively parallel applications are executed on distributed systems, where computing nodes are distant enough that the parallelization schemes must minimize communication and synchronization to achieve scalability. Mapping communica... » read more

Power Semiconductor Devices: Thermal Management and Packaging


A technical paper titled "Thermal management and packaging of wide and ultra-wide bandgap power devices: a review and perspective" was published by researchers at Virginia Polytechnic Institute and State University, U.S. Naval Research Laboratory, and Univ Lyon, CNRS. "This paper provides a timely review of the thermal management of WBG and UWBG power devices with an emphasis on packaged dev... » read more

Design Considerations and Recent Advancements in Chiplets (UC Berkeley/ Peking University)


A new technical paper titled "Automated Design of Chiplets" was published by researchers at UC Berkeley and Peking University. Abstract: "Chiplet-based designs have gained recognition as a promising alternative to monolithic SoCs due to their lower manufacturing costs, improved re-usability, and optimized technology specialization. Despite progress made in various related domains, the des... » read more

Surface-Activated ALD For Room-Temperature Bonding of Al2O3


A new technical paper titled "Room-temperature bonding of Al2O3 thin films deposited using atomic layer deposition" was published by researchers at Kyushu University. Abstract "In this study, room-temperature wafer bonding of Al2O3 thin films on Si thermal oxide wafers, which were deposited using atomic layer deposition (ALD), was realized using the surface-activated bonding (SAB) metho... » read more

Room-Temperature Metal Bonding Technology That Facilitates The Fabrication of 3D-ICs & 3D Integration With Heterogeneous Devices


A technical paper titled "Room-Temperature Direct Cu Semi-Additive Plating (SAP) Bonding for Chip-on-Wafer 3D Heterogenous Integration With μLED" was published by researchers at Tohoku University in Japan. Abstract: "This letter describes a direct Cu bonding technology to there-dimensionally integrate heterogeneous dielets based on a chip-on-wafer configuration. 100- μm -cubed blue μ LED... » read more

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