Understanding Fault Injection Attacks At The Pre-Silicon Level


A new technical paper titled "CRAFT: Characterizing and Root-Causing Fault Injection Threats at Pre-Silicon" was published by researchers at North Carolina State University. Abstract "Fault injection attacks represent a class of threats that can compromise embedded systems across multiple layers of abstraction, such as system software, instruction set architecture (ISA), microarchitecture, ... » read more

Effects Of Reduced Refresh Latency On RowHammer Vulnerability Of DDR4 DRAM Chips


A new technical paper titled "Understanding RowHammer Under Reduced Refresh Latency: Experimental Analysis of Real DRAM Chips and Implications on Future Solutions" was published by researchers at ETH Zurich, TOBB University of Economics and Technology, and University of Sharjah. Abstract "RowHammer is a major read disturbance mechanism in DRAM where repeatedly accessing (hammering) a row of... » read more

Wafer-Level Test Infrastructure for Higher Parallel Wafer Level Testing of SoC


A new technical paper titled "Design and Implementation of Test Infrastructure for Higher Parallel Wafer Level Testing of System-on-Chip" was published by researchers at Inha University and Teradyne. Abstract "Semiconductor companies have been striving to reduce their manufacturing costs. High parallelism is a key factor in reducing costs during wafer-level testing. Wafer testing is conduct... » read more

Synthesis Of An Ultrathin Vanadium Dioxide Film On A Flexible Substrate, Preserving Film’s Electrical Properties


A new technical paper titled "Strain-free thin film growth of vanadium dioxide deposited on 2D atomic layered material of hexagonal boron nitride investigated by their thickness dependence of insulator–metal transition behavior" was published by researchers at Osaka University and National Institute for Materials Science. Abstract "We report on the preparation of vanadium dioxide (VO2) ul... » read more

RISC-V High Performance Multicore and GPU SoC Platform For Safety Critical System


A new technical paper titled "A RISC-V Multicore and GPU SoC Platform with a Qualifiable Software Stack for Safety Critical Systems" published by researchers at Universitat Politecnica de Catalunya and Barcelona Supercomputing Center. Abstract "In the context of the Horizon Europe project, METASAT, a hardware platform was developed as a prototype of future space systems. The platform is bas... » read more

3D Stacked Device Architecture Enabled By BEOL-Compatible Transistors (Stanford et al.)


A new technical paper titled "Omni 3D: BEOL-Compatible 3-D Logic With Omnipresent Power, Signal, and Clock" was published by researchers at Stanford University, Intel Corporation and Carnegie Mellon University. Abstract "This article presents Omni 3D—a 3-D-stacked device architecture that is naturally enabled by back-end-of-line (BEOL)-compatible transistors. Omni 3D interleaves metal lay... » read more

SW-HW Co-Design Mitigation To Strengthen ASLR Against Microarchitectural Attacks (MIT)


A technical paper titled "Oreo: Protecting ASLR Against Microarchitectural Attacks" was published by researchers at MIT. Abstract "Address Space Layout Randomization (ASLR) is one of the most prominently deployed mitigations against memory corruption attacks. ASLR randomly shuffles program virtual addresses to prevent attackers from knowing the location of program contents in memory. Microa... » read more

Low-Temp Pressure-Assisted Liquid-Metal Printing for Oxide-TFTs


A new technical paper titled "Low-temperature pressure-assisted liquid-metal printing for β-Ga2O3 thin-film transistors" was published by researchers at UCSD and National Tsing Hua University. Abstract "Developing a low-temperature and cost-effective manufacturing process for energy-efficient and high-performance oxide-thin-film transistors (TFTs) is a crucial step toward advanci... » read more

Machine Learning-Based IR Drop Prediction Approach


A new technical paper titled "Estimating Voltage Drop: Models, Features and Data Representation Towards a Neural Surrogate" was published by researchers at KTH Royal Institute of Technology and Ericsson Research. ABSTRACT "Accurate estimation of voltage drop (IR drop) in modern Application-Specific Integrated Circuits (ASICs) is highly time and resource demanding, due to the growing complex... » read more

Design Space For The Device-Circuit Codesign Of NVM-Based CIM Accelerators (TSMC)


A new technical paper titled "Assessing Design Space for the Device-Circuit Codesign of Nonvolatile Memory-Based Compute-in-Memory Accelerators" was published by TSMC researchers. Abstract "Unprecedented penetration of artificial intelligence (AI) algorithms has brought about rapid innovations in electronic hardware, including new memory devices. Nonvolatile memory (NVM) devices offer one s... » read more

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