category: Technical Papers

category: IoT, Security & Automotive

Inter-Chiplet Interconnect Topologies On Organic And Glass Substrates
By Technical Paper Link - 29 Apr, 2025 - Comments: 0

A new technical paper titled "FoldedHexaTorus: An Inter-Chiplet Interconnect Topology for Chiplet-based Systems using Organic and Glass Substrates" was published by researchers at ETH Zurich. Abstract "Chiplet-based systems are rapidly gaining traction in the market. Two packaging options for such systems are the established organic substrates and the emerging glass substrates. These substr... » read more

On-Chiplet Framework for Verifying Physical Security and Integrity of Adjacent Chiplets
By Technical Paper Link - 29 Apr, 2025 - Comments: 0

A new technical paper titled "ChipletQuake: On-die Digital Impedance Sensing for Chiplet and Interposer Verification" was published by researchers at Worcester Polytechnic Institute. Abstract "The increasing complexity and cost of manufacturing monolithic chips have driven the semiconductor industry toward chiplet-based designs, where smaller and modular chiplets are integrated onto a singl... » read more

Controlled Shared Memory For Dynamically Controlling Data Communication Via Shared Memory Approaches (ASU, Intel)
By Technical Paper Link - 27 Apr, 2025 - Comments: 0

A new technical paper titled "Controlled Shared Memory (COSM) Isolation: Design and Testbed Evaluation" was published by researchers at Arizona State University and Intel Corporation. Abstract "Recent memory sharing approaches, e.g., based on the Compute Express Link (CXL) standard, allow the flexible high-speed sharing of data (i.e., data communication) among multiple hosts. In information... » read more

A Survey Of Digital Twins and Other Prototyping Technologies for Vehicles
By Technical Paper Link - 26 Apr, 2025 - Comments: 0

A new technical paper titled "Digital Twin Technologies for Vehicular Prototyping: A Survey" was published by researchers at Central Michigan University and University of Florida. Abstract "Digital Twin (DT) technology is widely regarded as one of the most promising tools for industry development, demonstrating substantial application across numerous cyber-physical systems. Gradually, this ... » read more

Impact Of Cryogenic Temps On The Minimum-Operating Voltage Of 5nm FinFETs-Based SRAM (IIT, UC Berkeley et al)
By Technical Paper Link - 25 Apr, 2025 - Comments: 0

A new technical paper titled "An Investigation of Minimum Supply Voltage of 5nm SRAM from 300K down to 10K" was published by researchers at Indian Institute of Technology, UC Berkeley and Munich Institute of Robotics and Machine Intelligence. Abstract "In this article, we present a comprehensive study of the impact of cryogenic temperatures on the minimum-operating voltage (Vmin) of 5 nm ... » read more

Differences In The Lithographic Impact Of Particles On The Pellicle Surface Depending On Type Of EUV Mask Pattern
By Technical Paper Link - 25 Apr, 2025 - Comments: 0

A new technical paper titled "Impact of Sn Particle-Induced Mask Diffraction on EUV Lithography Performance Across Different Pattern Types" was published by Hanyang University and Paul Scherrer Institute. Abstract "This study investigates the differences in the lithographic impact of particles on the pellicle surface depending on the type of extreme ultraviolet (EUV) mask pattern. Using a... » read more

Challenges of Chiplet Placement And Routing Optimization (KAIST)
By Technical Paper Link - 23 Apr, 2025 - Comments: 0

A new technical paper titled "Advanced Chiplet Placement and Routing Optimization considering Signal Integrity" was published by researchers at KAIST. Abstract: "This article addresses the critical challenges of chiplet placement and routing optimization in the era of advanced packaging and heterogeneous integration. We present a novel approach that formulates the problem as a signal integr... » read more

Hardware Security: Assessment Method For Attacks Using Real-World Cases (TU Wien, TÜV Austria)
By Technical Paper Link - 23 Apr, 2025 - Comments: 0

A new technical paper titled "The Pains of Hardware Security: An Assessment Model of Real-World Hardware Security Attacks" was published by researchers at TU Wien and TÜV Austria. "We review some of the publicly known HW attacks that have occurred and propose an assessment scheme for the attacks and the defense on hardware," states the paper. Find the technical paper here. April 2025. ... » read more

HW-based Heterogeneous Memory Management for LLM Inferencing (KAIST, Stanford Unversity)
By Technical Paper Link - 22 Apr, 2025 - Comments: 0

A new technical paper titled "Hardware-based Heterogeneous Memory Management for Large Language Model Inference" was published by researchers at KAIST and Stanford University. Abstract "A large language model (LLM) is one of the most important emerging machine learning applications nowadays. However, due to its huge model size and runtime increase of the memory footprint, LLM inferences suf... » read more

Single Transistor Memory Cell C2RAM Based On FDSOI For Quantum And Neuromorphic
By Technical Paper Link - 15 Apr, 2025 - Comments: 0

A new technical paper titled "An Energy Efficient Memory Cell for Quantum and Neuromorphic Computing at Low Temperatures" was published by researchers at Forschungszentrum Jülich, RWTH Aachen University and SOITEC. Abstract: "Efficient computing in cryogenic environments, including classical von Neumann, quantum, and neuromorphic systems, is poised to transform big data processing. The que... » read more

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