category: Transistors

category: IoT, Security & Automotive

Suitability of FeFET-Based CAM Cells For Storage-Class Memory, Under Junction Temperature Variations
By Technical Paper Link - 15 Jan, 2024 - Comments: 0

A technical paper titled “Ferroelectric Field Effect Transistors–Based Content-Addressable Storage-Class Memory: A Study on the Impact of Device Variation and High-Temperature Compatibility” was published by researchers at Fraunhofer Institute for Photonic Microsystems (IPMS) and Indian Institute of Technology Madras (IIT Madras). Abstract: "Hafnium oxide (HfO2)-based ferroelectric fiel... » read more

A Potentially CMOS Compatible Integration Of Reconfigurable FETs Based On Al-Si-Al Heterostructure Sheets
By Technical Paper Link - 11 Jan, 2024 - Comments: 0

A technical paper titled “Reconfigurable Si Field-Effect Transistors With Symmetric On-States Enabling Adaptive Complementary and Combinational Logic” was published by researchers at TU Vienna and Swiss Federal Laboratories for Materials Science and Technology. Abstract: "Reconfigurable field-effect transistors (RFETs), combining n-and p-type operation in a single device, have already sho... » read more

Summary Of The Progress In Beta-Phase Gallium Oxide Field-Effect Transistors
By Technical Paper Link - 11 Jan, 2024 - Comments: 0

A technical paper titled “Progress in Gallium Oxide Field-Effect Transistors for High-Power and RF Applications” was published by researchers at George Mason University and National Institute of Standards and Technology (NIST). Abstract: "Power electronics are becoming increasingly more important, as electrical energy constitutes 40% of the total primary energy usage in the USA and is exp... » read more

8-In-1 Reconfigurable Logic Gate (TU Dresden)
By Technical Paper Link - 03 Jan, 2024 - Comments: 0

A technical paper titled “The RGATE: an 8-in-1 Polymorphic Logic Gate Built from Reconfigurable Field Effect Transistors” was published by researchers at TU Dresden and NaMLab. Abstract: "We present the hardware implementation of a reconfigurable universal logic gate, that we call RGATE, able to deliver up to eight different logic functionalities and based on a symmetric four-transistors... » read more

Rapid Prototyping For Emerging Semiconductor Devices
By Technical Paper Link - 03 Jan, 2024 - Comments: 0

A technical paper titled “Generating Predictive Models for Emerging Semiconductor Devices” was published by researchers at TU Darmstadt and NaMLab. Abstract: "Circuit design requires fast and scalable models which are compatible to modern electronic design automation tools. For this task typically analytical compact models are preferred. However, for emerging device concepts with altered ... » read more

Quantum Confinement And Its Effect On The Thermoelectric Performance For Thermal Management
By Technical Paper Link - 03 Jan, 2024 - Comments: 0

A technical paper titled “Enhanced thermoelectric performance via quantum confinement in a metal oxide semiconductor field effect transistor for thermal management” was published by researchers at Sandia National Laboratories and Kansas State University. Abstract: "The performance of thermoelectric devices is gauged by the dimensionless figure of merit ZT. Improving ZT has proven to be a ... » read more

Nanoscale Reconfigurable Si Transistors (TU Wien, CNRS, UNC)
By Technical Paper Link - 20 Dec, 2023 - Comments: 0

A new technical paper titled "Nanoscale Reconfigurable Si Transistors: From Wires to Sheets and Unto Multi-Wire Channels" was published by researchers at TU Wien, CNRS, and University of North Carolina at Chapel Hill. Abstract: "In this work, bottom-up Al–Si–Al nanowire (NW) heterostructures are presented, which act as a prototype vehicle toward top-down fabricated nanosheet (NS) and ... » read more

Forward Body Biasing in Bulk Cryo-CMOS With Negligible Leakage (TU Delft)
By Technical Paper Link - 20 Dec, 2023 - Comments: 0

A new technical paper titled "Cryogenic-Aware Forward Body Biasing in Bulk CMOS" was published by researchers at QuTech, Tu Delft. Abstract "Cryogenic CMOS (cryo-CMOS) circuits are often hindered by the cryogenic threshold-voltage increase. To mitigate such an increase, a forward body biasing (FBB) technique in bulk CMOS is proposed, which can operate up to the nominal supply without prob... » read more

GAA NSFETs: ML for Device and Circuit Modeling
By Technical Paper Link - 30 Nov, 2023 - Comments: 0

A new technical paper titled "A Comprehensive Technique Based on Machine Learning for Device and Circuit Modeling of Gate-All-Around Nanosheet Transistors" was published by researchers at National Yang Ming Chiao Tung University. Abstract (excerpt) "Machine learning (ML) is poised to play an important part in advancing the predicting capability in semiconductor device compact modeling domai... » read more

Engineering chirality at wafer scale with ordered CNT architecture (Rice University and others)
By Technical Paper Link - 29 Nov, 2023 - Comments: 0

A new technical paper titled "Engineering chirality at wafer scale with ordered carbon nanotube architectures" was published by researchers at Rice University, University of Utah, J.A. Woollam Co. and Tokyo Metropolitan University. Abstract "Creating artificial matter with controllable chirality in a simple and scalable manner brings new opportunities to diverse areas. Here we show two su... » read more

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