category: Top Stories

category: IoT, Security & Automotive

Balancing Parallel Test Productivity With Yield & Cost
By Anne Meixner - 12 Nov, 2024 - Comments: 0

Parallel test is used for nearly every device produced by fabs and OSATs, but it can reduce yield and increase the cost of test boards and operations. This is a well-understood tradeoff for ensuring consistent test accuracy across multiple sites and reducing test time. Collectively, ATEs and multi-site test boards — DUT interface boards (DIBs), probe cards, and load boards — significantl... » read more

Metrology Advances Step Up To Sub-2nm Device Node Needs
By Laura Peters - 15 Oct, 2024 - Comments: 0

Metrology and inspection are dealing with a slew of issues tied to 3D measurements, buried defects, and higher sensitivity as device features continue to shrink to 2nm and below. This is made even more challenging due to increasing pressure to ramp new processes more quickly. Metrology tool suppliers must exceed current needs by a process node or two to ensure solutions are ready to meet tig... » read more

New Challenges In IC Reliability
By Ed Sperling - 15 Oct, 2024 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss reliability of chips, how it is changing, and where the new challenges are, with Steve Pateras, vice president of marketing and business development at Synopsys; Noam Brousard, vice president of solutions engineering at proteanTecs; Harry Foster, chief verification scientist at Siemens EDA; and Jerome Toublanc, high-tech soluti... » read more

Signals In The Noise: Tackling High-Frequency IC Test
By Gregory Haley - 15 Oct, 2024 - Comments: 0

The need for high-frequency semiconductor devices is surging, fueled by growing demand for advanced telecommunications, faster sensors, and increasingly autonomous vehicles. The advent of millimeter-wave communication in 5G and 6G is pushing manufacturers to develop chips capable of handling frequencies that were once considered out of reach. However, while these technologies promise faster ... » read more

Defect Challenges Grow At The Wafer Edge
By Laura Peters - 10 Sep, 2024 - Comments: 0

Reducing defects on the wafer edge, bevel, and backside is becoming essential as the complexity of developing leading-edge chips continue to increase, and where a single flaw can have costly repercussions that span multiple processes and multi-chip packages. This is made more difficult by the widespread rollout of such processes as hybrid bonding, which require pristine surfaces, and the gro... » read more

Promises and Perils of Parallel Test
By Anne Meixner - 10 Sep, 2024 - Comments: 1

Testing multiple devices at the same time is not providing the equivalent reduction in overall test time due to a combination of test execution issues, the complexity of the devices being tested, and the complex tradeoffs required for parallelism. Parallel testing is now the norm — from full wafer probe DRAM testing with thousands of dies to two-site testing for complex, high-performance c... » read more

Standardizing Defect Coverage In Analog/Mixed Signal Test
By Gregory Haley - 10 Sep, 2024 - Comments: 0

A newly drafted IEEE standard will bring more consistency to defect metrics in analog/mixed (AMS) designs, a long-overdue step that has become too difficult to ignore in the costly heterogeneous assemblies being deployed inside of data centers and mobile devices. Standardizing analog is no simple feat due to the legacy approach to AMS design, and this is not the first attempt at improving te... » read more

AI/ML’s Role In Design And Test Expands
By Laura Peters - 06 Aug, 2024 - Comments: 1

The role of AI and ML in test keeps growing, providing significant time and money savings that often exceed initial expectations. But it doesn't work in all cases, sometimes even disrupting well-tested process flows with questionable return on investment. One of the big attractions of AI is its ability to apply analytics to large data sets that are otherwise limited by human capabilities. In... » read more

Metrology And Inspection For The Chiplet Era
By Gregory Haley - 06 Aug, 2024 - Comments: 0

New developments and innovations in metrology and inspection will enable chipmakers to identify and address defects faster and with greater accuracy than ever before, all of which will be required at future process nodes and in densely packed assemblies of chiplets. These advances will affect both front-end and back-end processes, providing increased precision and efficiency, combined with a... » read more

Driving Cost Lower and Power Higher With GaN
By Anne Meixner - 06 Aug, 2024 - Comments: 0

Gallium nitride is starting to make broader inroads in the lower-end of the high-voltage, wide-bandgap power FET market, where silicon carbide has been the technology of choice. This shift is driven by lower costs and processes that are more compatible with bulk silicon. Efficiency, power density (size), and cost are the three major concerns in power electronics, and GaN can meet all three c... » read more

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