category: Top Stories

category: IoT, Security & Automotive

Mission-Critical Devices Drive System-Level Test Expansion
By Laura Peters - 11 Jul, 2023 - Comments: 0

System-level testing is becoming essential for testing complex and increasingly heterogeneous chips, driven by rising demand for reliable parts in safety- and mission-critical applications. More and more chip manufacturers are jumping on the SLT bandwagon for high-volume manufacturing (HVM) of these devices. Unlike ATE and packaged device testing, SLT mimics actual semiconductor system opera... » read more

Governments Begin To Shape Metrology Directions
By Gregory Haley - 11 Jul, 2023 - Comments: 0

Disruptions to the global semiconductor supply chain caused by the COVID-19 pandemic had a severe impact in nearly every sector of the worldwide economy, and especially the worldwide semiconductor market. Due to a shortage of chips, the global auto industry alone suffered a $210 billion loss in 2021, accompanied by a 7.7 million unit production drop, according to AlixPartners, a global consulti... » read more

Pinpointing Timing Delays in Complex SoCs
By Anne Meixner - 11 Jul, 2023 - Comments: 0

Telemetry circuits are becoming a necessity in complex heterogeneous chips and packages to show how these devices are behaving post-production, but fusing together relevant data to identify the sources of problems adds its own set of challenges. In the past, engineering teams could build margin into chips to offset any type of variation. But at advanced nodes and in advanced packages, tolera... » read more

From Lab To Fab: Increasing Pressure To Fuse IC Processes
By Gregory Haley - 06 Jun, 2023 - Comments: 0

Test, metrology, and inspection are essential for both the lab and the fab, but fusing them together so that data created in one is easily transferred to the other is a massive challenge. The chip industry has been striving to bridge these separate worlds for years, but the economics, speed, and complexity of change require a new approach. The never-ending push toward smaller, better-defined... » read more

Journey From Cell-Aware To Device-Aware Testing Begins
By Laura Peters - 06 Jun, 2023 - Comments: 0

Early results of using device-aware testing on alternative memories show expanded test coverage, but this is just the start. Once the semiconductor industry realized that it was suffering from device failures even when test programs achieved 100% fault coverage, it went about addressing this disconnect between the way defects manifest themselves inside devices and the commonly used fault mod... » read more

Ramping Up Power Electronics For EVs
By Anne Meixner - 06 Jun, 2023 - Comments: 0

The rapid acceleration of the power devices used in electric vehicles (EVs) is challenging chipmakers to adequately screen the ICs that power these vehicles.[1] While progress toward autonomous driving is grabbing the public’s attention, the electrification of transportation systems is progressing quietly. For the automotive industry, this shift involves a mix of electronic components. Amo... » read more

How Metrology Tools Stack Up In 3D NAND Devices
By Laura Peters - 15 May, 2023 - Comments: 0

Multiple innovations in semiconductor processing are needed to enable 3D NAND bit density increases of about 30% per year at ever-decreasing cost per bit, all of which will be required to meet the nonvolatile storage needs of the big data era. 3D NAND is the first truly three-dimensional device in production. It is both a technology driver for new metrology methods and a significant part of ... » read more

Pinpointing Timing Delays Can Improve Chip Reliability
By Anne Meixner - 09 May, 2023 - Comments: 0

Growing pressure to improve IC reliability in safety- and mission-critical applications is fueling demand for custom automated test pattern generation (ATPG) to detect small timing delays, and for chip telemetry circuits that can assess timing margin over a chip's lifetime. Knowing the timing margin in signal paths has become an essential component in that reliability. Timing relationships a... » read more

3D Structures Challenge Wire Bond Inspection
By Karen Heyman - 09 May, 2023 - Comments: 1

Adding more layers in packages is making it difficult, and sometimes impossible, to inspect wire bonds that are deep within the different layers. Wire bonds may seem like old technology, but it remains the bonding approach of choice for a broad swath of applications. This is particularly evident in automotive, industrial, and many consumer applications, where the majority of chips are not de... » read more

Optimizing Scan Test For Complex ICs
By Gregory Haley - 09 May, 2023 - Comments: 0

As chips become more heterogeneous with more integrated functionality, testing them presents increasing challenges — particularly for high-speed system-on-chip (SoC) designs with limited test pin availability. In addition, the complexity of emerging packages like 3D and chiplets necessitates comprehensive new solutions that can provide faster results at multiple stages in the silicon lifec... » read more

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