How Long Will FinFETs Last? (Part 3)


Semiconductor Engineering sat down to discuss how long [getkc id="185" kc_name="FinFET"]s will last and where we will we go next with Vassilios Gerousis, Distinguished Engineer at [getentity id="22032" e_name="Cadence"]; Juan Rey, Sr. Director of Engineering for Calibre R&D at [getentity id="22017" e_name="Mentor Graphics"]; Kelvin Low, Senior Director Foundry Marketing at [getentity id="22... » read more

Manufacturing Of Next-Generation Channel Materials


One of the many challenges for the IC developers is to change the channel material to increase transistor mobility. But what about manufacturing? Can LED-style epitaxy be migrated to high-volume silicon manufacturing? “The use of Ge and InGaAs quantum wells is an extension of the current strained Si strategy," said Aaron Thean, vice president of process technologies and director of the log... » read more

Gaps Remain For EUV Masks


Extreme ultraviolet (EUV) lithography is once again at a critical juncture. The oft-delayed technology is now being targeted for 7nm. But there are still a number of technologies that must come together before EUV is inserted into mass production at that node. First, the EUV source must generate more power. Second, tool uptime must improve. Third, the industry needs better EUV resists. A... » read more

Power Estimation: Early Warning System Or False Alarm?


Semiconductor Engineering sat down with a large panel of experts to discuss the state of power estimation and to find out if the current levels of accuracy are sufficient to being able to make informed decisions. Panelists included: Leah Schuth, director of technical marketing in the physical design group at [getentity id="22186" comment="ARM"]; Vic Kularni, senior vice president and general ma... » read more

Executive Insight: Lip-Bu Tan


Lip-Bu Tan, president and CEO of Cadence, sat down with Semiconductor Engineering to talk about consolidation, Moore's Law, and where the opportunities are in the IoT and automotive markets. What follows are excerpts of that conversation. SE: What are the big concerns for the semiconductor industry in general, and EDA in particular? Tan: Top on my list is all the consolidation that's goin... » read more

Resist Sensitivity, Source Power, And EUV Throughput


In a recent article, I quoted 15 mJ/cm2 as the target sensitivity for EUV photoresists, and discussed the throughput that could be achieved at various source power levels. However, as a commenter on that article pointed out, reaching the 15 mJ/cm² target while also meeting line roughness requirements is itself a challenging problem. Because of the high energy of EUV photons, a highly sensitive... » read more

Mask Metrology Challenges Grow


Photomasks are becoming more complex at each node. In fact, masks are moving from traditional shapes to non-orthogonal patterns and complex shapes, such as curvilinear mask patterns. To measure patterns and shapes on the mask, photomask makers use traditional critical-dimension scanning electron microscopes (CD-SEMs). In general, the CD-SEM, the workhorse metrology tool in the mask shop, use... » read more

Survey: Mask Complexity To Increase


The eBeam Initiative today released its annual members’ perceptions survey, a set of results that reveals some new and surprising data about EUV, multi-beam and photomask technology. As part of the results in the new survey, there is a growing level of optimism for the implementation of extreme ultraviolet (EUV) lithography in high-volume manufacturing, as compared to last year’s results... » read more

Is The 2.5D Supply Chain Ready?


A handful of big semiconductor companies began taking the wraps off 2.5D and fan-out packaging plans in the past couple of weeks, setting the stage for the first major shift away from Moore's Law in 50 years. Those moves coincide with reports of commercial [getkc id="82" kc_name="2.5D"] chips from chip assemblers and foundries that are now under development. There have been indications for... » read more

Is HW Or SW Running the Show?


In the past, hardware was designed and then passed over to the software team for them to add their contribution to the product. This worked when the amount of software content was small and the practice did not significantly contribute to product delays. Over time, the software content grew and today it is generally accepted that software accounts for more product expense than hardware, takes l... » read more

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