category: Top Stories

category: Auto, Security & Edge AI

Faster Time To Yield
By Ed Sperling - 23 Aug, 2016 - Comments: 2

Michael Jamiolkowski, president and CEO of Coventor, sat down with Semiconductor Engineering to talk about ways improve yield ramp and optimize designs. What follows are excerpts of that conversation. SE: Why does it take so long to get a chip all the way through to manufacturing? Jamiolkowski: There are three parts to that. There is a research side. You want to be able to explore new th... » read more

Deeper Inside Intel
By Mark LaPedus - 22 Aug, 2016 - Comments: 5

Mark Bohr, senior fellow and director of process architecture and integration at Intel, and Zane Ball, vice president in the Technology and Manufacturing Group at Intel and co-general manager of Intel Custom Foundry, sat down with Semiconductor Engineering to discuss the future directions of transistors, process technology, the foundry business and packaging. What follows are excerpts of those ... » read more

How Small Will Transistors Go?
By Mark LaPedus - 18 Aug, 2016 - Comments: 1

By Mark LaPedus & Ed Sperling There is nearly universal agreement that Moore’s Law is slowing down. But whether it will truly end, or just become too expensive and less relevant—and what will supplant device scaling—are the subject of some far-reaching research and much discussion. Semiconductor Engineering sat down with each of the leaders of three top research houses—[getent... » read more

China’s Capital Equipment Market To Boom
By Jeff Dorsch - 18 Aug, 2016 - Comments: 1

The worldwide semiconductor capital equipment market declined 3% last year to $36.53 billion from 2014’s $37.5 billion, but inside China the story was significantly different. Capital equipment sales there increased by 12% in 2015, to $4.9 billion. In fact, only Japan showed a higher growth rate last year, of 31%, according to figures from [getentity id="22821" comment="SEMI"] and the Semi... » read more

Mask Maker Worries Grow
By Mark LaPedus - 18 Aug, 2016 - Comments: 2

Leading-edge photomask makers face a multitude of challenges as they migrate from the 14nm node and beyond. Mask making is becoming more challenging and expensive at each node on at least two fronts. On one front, mask makers must continue to invest in the development of traditional optical masks at advanced nodes. On another front, several photomask vendors are preparing for the possible ra... » read more

What Transistors Will Look Like At 5nm
By Mark LaPedus - 18 Aug, 2016 - Comments: 3

Chipmakers are currently ramping up 16nm/14nm finFET processes, with 10nm and 7nm just around the corner. The industry also is working on 5nm. TSMC hopes to deliver a 5nm process by 2020. GlobalFoundries, Intel and Samsung are doing R&D for that node. But 5nm technology presents a multitude of unknowns and challenges. For one thing, the exact timing and specs of 5nm remain cloudy. The... » read more

Focus Shifting To Photonics
By Ed Sperling - 17 Aug, 2016 - Comments: 4

Silicon photonics finally appears ready for prime time, after years of unfulfilled expectations and a vision that stretches back at least a couple decades. The biggest challenge has been the ability to build a light source directly into the silicon process, rather than trying to add one onto a chip after manufacturing. [getentity id="22846" e_name="Intel"] today said it has achieved that mi... » read more

Optimization Challenges For 10nm And 7nm
By Brian Bailey - 17 Aug, 2016 - Comments: 0

Optimization used to be a simple timing against area tradeoff but not anymore. As we go to each new node, the tradeoffs become more complicated involving additional aspects of the design that used to be dealt with in isolation. Semiconductor Engineering sat down to discuss these issues with Krishna Balachandran, director of product management for low power products at [getentity id="22032" ... » read more

New Architectures, Approaches To Speed Up Chips
By Ed Sperling - 15 Aug, 2016 - Comments: 2

The need for speed is back. An explosion in the amount of data that needs to be collected and processed is driving a new wave of change in hardware, software and overall system design. After years of emphasizing power reduction, performance has re-emerged as a top concern in a variety of applications such as smarter cars, wearable devices and cloud data centers. But how to get there has cha... » read more

Designing SoC Power Networks
By Brian Bailey - 11 Aug, 2016 - Comments: 0

Designing a power network for a complex SoC is becoming critical for the success of the product, but most chips are still using old techniques that are ill-suited to the latest fabrication technologies, resulting in an expensive, overdesigned product. Not only is the power network as designed too large, but this has several knock-on effects that impact area, timing and power. In the first pa... » read more

← Older posts Newer posts →

  • Sponsors

  • Standards/Organizations

About

Navigation

Connect With Us

Copyright ©2013-2026 SMG   |  Terms of Service  |  Privacy Policy