category: Top Stories

category: Auto, Security & Edge AI

Cars, Security, And HW-SW Co-Design
By Jeff Dorsch - 31 Aug, 2016 - Comments: 0

Semiconductor Engineering sat down to discuss parallel hardware/software design with Johannes Stahl, director of product marketing, prototyping and FPGA, [getentity id="22035" e_name="Synopsys"]; [getperson id="11411" comment="Bill Neifert"], director of models technology, [getentity id="22186" comment="ARM"]; Hemant Kumar, director of ASIC design, Nvidia; and Scott Constable, senior member of ... » read more

Context Is Everything
By Ann Mutschler - 29 Aug, 2016 - Comments: 0

With consumer and industrial IoT applications, the importance of system context to IC vendors is paramount. No more are the days of developing a chip in isolation; close partnership with systems companies is de rigueur as they provide the use case data that is foundational to development of systems that work. While this makes sense in a smartphone, it’s significantly harder to achieve in a... » read more

Will Hypervisors Protect Us?
By Brian Bailey - 25 Aug, 2016 - Comments: 2

Another day, another car hacked and another report of a data breach. The lack of security built into electronic systems has made them a playground for the criminal world, and the industry must start becoming more responsive by adding increasingly sophisticated layers of protection. In this, the first of a two-part series, Semiconductor Engineering examines how hypervisors are entering the embed... » read more

Can Analog And Digital Get Along Better?
By Ann Mutschler - 25 Aug, 2016 - Comments: 1

How to bridge analog and digital is getting renewed attention as the amount of analog content that needs to be processed balloons with consumer and industrial IoT applications. Solving that problem isn’t going to be easy, though. To begin with, digital designers view designs in terms of voltages. Analog designers, in contrast, look at currents. “Unless you can analyze an [getkc id="37... » read more

Putting Design Back Into DFT
By Brian Bailey - 25 Aug, 2016 - Comments: 0

Test always has been a delicate balance between cost and quality, but there are several changes happening in the industry that might cause a significant alteration in strategy. Part one of this two part series about [getkc id="47" comment="Design for Test (DFT)"] looked at changes in areas such as automotive, where built in self-test is becoming a mandated part of the design process. This co... » read more

FPGA Prototyping Gains Ground
By Jeff Dorsch - 25 Aug, 2016 - Comments: 0

FPGA technology for design prototypes is making new inroads as demands increase for better integration between hardware and software. [gettech id="31071" comment="FPGA"] prototyping, also known as physical prototyping, has been supported by all of the major EDA players for some time, and it has been considered an essential tool for the largest chipmakers, along with emulation and simulation.... » read more

Stepping Back From Scaling
By Ed Sperling - 24 Aug, 2016 - Comments: 0

Architectures, packaging and software are becoming core areas for semiconductor research and development, setting the stage for a series of shifts that will impact a large swath of the semiconductor industry. While there is still demand from the largest chipmakers for increased density at the next process node, the underlying economics for foundries, equipment vendors and IP developers are f... » read more

The Future Of Memory
By Ed Sperling - 24 Aug, 2016 - Comments: 0

Semiconductor Engineering sat down to discuss future memory with Frank Ferro, senior director of product management for memory and interface IP at Rambus; Marc Greenberg, director of product marketing at Synopsys; and Lisa Minwell, eSilicon's senior director of IP marketing. What follows are excerpts of that conversation. To view part 1, click here. Part 2 is here. SE: What’s the next big ... » read more

Faster Time To Yield
By Ed Sperling - 23 Aug, 2016 - Comments: 2

Michael Jamiolkowski, president and CEO of Coventor, sat down with Semiconductor Engineering to talk about ways improve yield ramp and optimize designs. What follows are excerpts of that conversation. SE: Why does it take so long to get a chip all the way through to manufacturing? Jamiolkowski: There are three parts to that. There is a research side. You want to be able to explore new th... » read more

Deeper Inside Intel
By Mark LaPedus - 22 Aug, 2016 - Comments: 5

Mark Bohr, senior fellow and director of process architecture and integration at Intel, and Zane Ball, vice president in the Technology and Manufacturing Group at Intel and co-general manager of Intel Custom Foundry, sat down with Semiconductor Engineering to discuss the future directions of transistors, process technology, the foundry business and packaging. What follows are excerpts of those ... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2026 SMG   |  Terms of Service  |  Privacy Policy