Fab Issues At 7nm And 5nm


The race toward the 7nm logic node officially kicked off in July, when IBM Research, GlobalFoundries and Samsung jointly rolled out what the companies claim are the industry’s first 7nm test chips with functional transistors. They're not alone, of course. Intel and TSMC also are racing separately to develop 7nm technology. And in the R&D labs, chipmakers also are working on technologies f... » read more

Rethinking Manufacturing Models


The perennial uncertainty surrounding EUV lithography and complications stemming from the most advanced nodes are creating a domino effect across the semiconductor industry. Rather than stalling the market, though, which is what happened with the transition to 20nm, vendors now are accelerating their product rollouts and adjusting business plans to capitalize on those delays. That includes m... » read more

Inside Samsung’s Foundry Biz


Semiconductor Engineering sat down to talk about the foundry business, process technology, design and other topics with Hong Hao, senior vice president of the foundry business at [getentity id="22865" e_name="Samsung Semiconductor"]; and Kelvin Low, senior director of foundry marketing at Samsung Semiconductor. What follows are excerpts of that discussion. SE: The foundry business has alway... » read more

Challenges At Advanced Nodes


Semiconductor Engineering sat down to discuss finFETs, 22nm FD-SOI and how the how the market will segment over the next few years with Marie Semeria, CEO of [getentity id="22192" e_name="Leti"]; Patrick Soheili, vice president of product management and corporate development at [getentity id="22242" e_name="eSilicon"]; Paul Boudre, CEO of Soitec; and Subramani Kengeri, vice president of global ... » read more

What Will 7nm And 5nm Look Like?


Citing an assortment of undisclosed manufacturing issues, Intel in July pushed out the introduction of its 10nm chip and process technology to the second half of 2017. This is roughly six or more months later than expected. With the delay at 10nm, [getentity id="22846" e_name="Intel"] also pushed out its process cadence from 2 to 2.5 years. Other foundries, meanwhile, are struggling to keep ... » read more

The Future Of Moore’s Law


Semiconductor Engineering sat down to discuss the future of Moore's Law with Jan Rabaey, Donald O. Pederson distinguished professor at [getentity id="22165" comment="UC Berkeley"]; Lucio Lanza, managing director of Lanza techVentures; Subramani Kengeri, vice president of advanced technology architecture at GlobalFoundries; Charlie Cheng, CEO of [getentity id="22135" e_name="Kilopass Technology"... » read more

How Much Security Is Enough?


Semiconductor Engineering sat down to discuss the current state of [getkc id="223" kc_name="security"] and what must be done in the future, with Denis Noël, head of cyber security solutions at [getentity id="22499" e_name="NXP"]; Serge Leef, vice president of new ventures at [getentity id="22017" e_name="Mentor Graphics"]; Andreas Kuehlman, senior vice president and general manager of the soft... » read more

Speeding Up Analog


Semiconductor Engineering sat down to discuss analog design and how to speed up analog circuits with Kurt Shuler, vice president of marketing at Arteris; Bernard Murphy, CTO at Atrenta; Wilbur Luo, senior group director, product management for custom IC and PCB at Cadence; Brad Hoskins, director, IC design, microcontrollers at Freescale; and Jeff Miller, product manager at Tanner EDA. What foll... » read more

Power Breaks Everything


The emphasis on lowering power in everything from wearable electronics to data centers is turning into a perfect storm for the semiconductor ecosystem. Existing methodologies need to be fixed, techniques need to be improved, and expectations need to be adjusted. And even then the problems won't go away. In the past, most issues involving power—notably current leakage, physical effects such... » read more

Moore’s Law Reset?


GlobalFoundries today took the wraps off its 22nm FD-SOI process, promising to extend Moore's Law technologically without altering the economic equation—at least for the next couple of process nodes. Subramani Kengeri, vice president of global design solutions at [getentity id="22819" comment="GlobalFoundries"], said 22nm FD-SOI will provide the same 30% improvement in PPA that has been c... » read more

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