category: Top Stories

category: IoT, Security & Automotive

Bug, Flaw, Or Cyberattack?
By Ann Mutschler - 02 Nov, 2023 - Comments: 0

The lines between counterfeiting, security, and design flaws are becoming increasingly difficult to determine in advanced packages and process nodes, where the number of possible causes of unusual behavior grow exponentially with the complexity of a device. Strange behavior may be due to a counterfeit part, including one that contains a trojan. Or it may be the result of a cyberattack. It al... » read more

For SDVs, Software Is The Biggest Challenge
By John Koon - 02 Nov, 2023 - Comments: 0

Software-defined vehicles (SDVs) involve far more than just OTA applications enabling software upgrades over the air. Software that will manage hundreds of ECUs and other functions within the vehicle is expected to grow beyond hundreds of millions of lines of code, possibly making SDV software development the number one challenge in automotive design. The benefits of SDVs, such as easy updat... » read more

Data Leakage In Heterogeneous Systems
By Ed Sperling - 02 Nov, 2023 - Comments: 0

Semiconductor Engineering sat down with Paul Chou, senior director of security architecture at NVIDIA, to discuss data leakage in heterogeneous designs. What follows are excerpts of that one-on-one interview, which was held in front of a live audience at the Hardwear.io conference. SE: We think about hardware in terms of a chip, but increasingly there is data moving through different systems... » read more

Isolating Critical Data In Failure Analysis
By Anne Meixner - 01 Nov, 2023 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss traceability and the lack of data needed to perform root cause analysis with Frank Chen, director of applications and product management at Bruker Nano Surfaces & Metrology; Mike McIntyre, director of product management in the Enterprise Business Unit at Onto Innovation; Kamran Hakim, ASIC reliability engineer at Teradyne... » read more

What Will That Chip Cost?
By Brian Bailey - 30 Oct, 2023 - Comments: 1

In the past, analysts, consultants, and many other experts attempted to estimate the cost of a new chip implemented in the latest process technology. They concluded that by the 3nm node, only a few companies would be able to afford them — and by the time they got into the angstrom range, probably nobody would. Much has changed over the past few process nodes. Increasing numbers of startups... » read more

Anatomy Of A System Simulation
By Brian Bailey - 26 Oct, 2023 - Comments: 0

The semiconductor industry has greatly simplified analysis by consolidating around a small number of models and abstractions, but that capability is breaking down both at the implementation level and at the system level. Today, the biggest pressure is coming from the systems industry, where the electronic content is a small fraction of what must be integrated together. Systems companies tend... » read more

Rethinking Design, Workflow For 3D
By Karen Heyman - 26 Oct, 2023 - Comments: 0

In the 3D world, where NAND has hundreds of layers and packages come in intricate stacks, fresh graduates and veteran engineers alike are being confronted with design challenges that require a rethinking of both classic designs and traditional workflows, but without breaking the laws of physics. “There are pockets of things that have been on 3D for quite some time,” said Kenneth Larson, ... » read more

Making Connections In 3D Heterogeneous Integration
By Ann Mutschler - 26 Oct, 2023 - Comments: 0

Activity around 3D heterogeneous integration (3DHI) is heating up, driven by growing support from governments, the need to add more features and compute elements into systems, and a widespread recognition that there are better paths forward than packing everything into a single SoC at the same process node. The leading edge of chip design has changed dramatically over the last few years. Int... » read more

Navigating EDA Vendor Cloud Options
By Ann Mutschler - 25 Oct, 2023 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss the challenges of cost-dependent cloud decisions, and how to navigate between different EDA vendor clouds options with Philip Steinke, fellow, CAD infrastructure and physical design at AMD; Mahesh Turaga, vice president of business development for cloud at Cadence Design Systems; Richard Ho, vice president hardware engineering ... » read more

Gearing Up For Hybrid Bonding
By Laura Peters - 23 Oct, 2023 - Comments: 2

Hybrid bonding is becoming the preferred approach to making heterogeneous integration work, as the semiconductor industry shifts its focus from 2D scaling to 3D scaling. By stacking chiplets vertically in direct wafer-to-wafer bonds, chipmakers can leapfrog attainable interconnection pitch from 35µm in copper micro-bumps to 10µm or less. That reduces signal delay to negligible levels and e... » read more

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