Near-Threshold Computing Gets A Boost


Near-threshold computing has long been used for power-sensitive devices, but some surprising, unrelated advances are making it much easier to deploy. While near-threshold logic has been an essential technique for applications with the lowest power consumption, it always has been difficult to use. That is changing, and while it is unlikely to become a mainstream technique, it is certainly bec... » read more

How Quickly Can SiC Ramp?


Device makers across the globe are ramping silicon carbide (SiC) manufacturing, with growth set to really take off starting in 2024. It’s been almost five years since Tesla and STMicroelectronics threw down the gauntlet with SiC in the Model 3. Now, no one doubts the market pull for electric vehicles, but consumers are still clamoring for better range and faster charging. SiC devices are a... » read more

Hybrid Bonding Moves Into The Fast Lane


The industry’s unquenchable thirst for I/O density and faster connections between chips, particularly logic and cache memory, is transforming system designs to include 3D architectures, and hybrid bonding has become an essential component in that equation. Hybrid bonding involves die-to-wafer or wafer-to-wafer connection of copper pads that carry power and signals and the surrounding diele... » read more

New Materials Open Door To New Devices


Integrating 2D materials into conventional semiconductor manufacturing processes may be one of the more radical changes in the chip industry’s history. While there is pain and suffering associated with the introduction of any new materials in semiconductor manufacturing, transition metal dichalcogenides (TMDs) support a variety of new device concepts, including BEOL transistors and single-... » read more

Telecare Challenges: Secure, Reliable, Lower Power


The adoption of telecare using a variety of connected digital devices is opening the door to much more rapid response to medical emergencies, as well as more consistent monitoring, but it also is adding new challenges involving connectivity, security, and power consumption. Telecare has been on the horizon for the better part of two decades, but it really began ramping with improvements in s... » read more

Heterogenous Integration Creating New IP Opportunities


The design IP market has long been known for constant change and evolution, but the industry trend toward heterogenous integration and chiplets is creating some new challenges and opportunities. Companies wanting to stake out a claim in this area have to be nimble, because there will be many potential standards introduced, and they are likely to change quickly as the industry explores what is r... » read more

Using AI To Speed Up Edge Computing


AI is being designed into a growing number of chips and systems at the edge, where it is being used to speed up the processing of massive amounts of data, and to reduce power by partitioning and prioritization. That, in turn, allows systems to act upon that data more rapidly. Processing data at the edge rather than in the cloud provides a number of well-documented benefits. Because the physi... » read more

Data Management Evolves


Semiconductor Engineering sat down to discuss data management challenges with Jerome Toublanc, business development executive at Ansys; Kam Kittrell, vice president of product management in the Digital & Signoff Group at Cadence; Simon Rance, vice president of marketing at Cliosoft; Rob Conant, vice president of software and ecosystem at Infineon Technologies; and Michael Munsey, senior dir... » read more

Customization, Heterogenous Integration, And Brute Force Verification


Semiconductor Engineering sat down to discuss why new approaches are required for heterogeneous designs, with Bari Biswas, senior vice president for the Silicon Realization Group at Synopsys; John Lee, general manager and vice president of the Ansys Semiconductor business unit; Michael Jackson, corporate vice president for R&D at Cadence; Prashant Varshney, head of product for Microsoft Azu... » read more

What Future Processors Will Look Like


Mark Papermaster, CTO at AMD, sat down with Semiconductor Engineering to talk about architectural changes that are required as the benefits of scaling decrease, including chiplets, new standards for heterogeneous integration, and different types of memory. What follows are excerpts of that conversation. SE: What does a processor look like in five years? Is it a bunch of chips in a package? I... » read more

← Older posts Newer posts →