3D NAND Is A Reality – What’s Next?

By Gill Lee - 02 Dec, 2013 - Comments: 0

One of the biggest developments taking place in the semiconductor industry is the emergence of 3D NAND memory technology. Products are available today that feature 3D NAND devices. It has taken years to become a reality — since Toshiba first discussed the concept of 3D NAND at the VLSI Symposium in 2007 – and now it is poised to replace planar NAND flash memory for storage. The path that... » read more

Materials Innovation Key To Enabling Next-Generation Mobile Devices

By Kathryn Ta - 09 Sep, 2013 - Comments: 0

By Kathryn Ta There’s a lot of excitement building regarding several new mobile product announcements on the horizon, including a concept smartwatch, a new phablet and a new smartphone. These products are sure to be on a lot of consumers’ wish lists this holiday season, and users will expect them to have a sleeker look and feel, while running applications instantly, providing all-day batte... » read more

What Is Going On With Sub-20nm Flash?

By Gill Lee - 15 Aug, 2013 - Comments: 0

By Gill Lee This week I’ll be participating in a panel discussion at the Flash Memory Summit in Santa Clara, CA. The panel’s topic, Flash Below 20nm: What is Coming and When?, couldn’t be more timely. Particularly in light of a leading NAND manufacturer’s recent announcement that they will begin mass production of the semiconductor industry’s first 3D vertical NAND flash memory later... » read more

Mobility Gets A Boost With Expanded Epi Applications

By Applied Materials Writers - 17 Jul, 2013 - Comments: 0

By Jeremy Zelenko Even as industry moves into the era of the high k metal gate (HKMG) and FinFET transistor, chipmakers continue to seek ways to improve device performance. One of the latest advances and the subject of an Applied Materials announcement made today is to extend epitaxial deposition from PMOS to NMOS transistors. Implementing an NMOS epitaxy (epi) process in addition to the estab... » read more

Overcoming Shallow Trench Isolation

By Kathryn Ta - 20 Jun, 2013 - Comments: 0

By Kathryn Ta To prevent electrical current leaking between adjacent transistors, state-of-the-art microchips feature shallow trench isolation (STI) to isolate transistors from each other. Key steps in the STI process involve etching a pattern of trenches in the silicon, depositing dielectric materials to fill the trenches, and removing the excess dielectric using technologies such as chemical... » read more

President Obama Visits Applied Materials

By Applied Materials Writers - 16 May, 2013 - Comments: 0

By John Kania [caption id="attachment_8398" align="alignnone" width="518" caption="Applied Materials CEO Mike Splinter with President Barack Obama as they tour the Austin manufacturing clean room and hear from Applied employee Nilam D. Bhakta-Sahib about the complex chip making process. "][/caption] President Obama rode Air Force One into Austin, Texas, to shine a spotlight on the import... » read more

Nanoscale Wiring

By Kathryn Ta - 21 Mar, 2013 - Comments: 0

By Kathryn Ta The TEM image (below) taken at Applied Materials’ Maydan Technology Center shows a series of 20nm-wide trenches in cross section. These tiny structures – about 1/5000th of the diameter of an average human hair – are similar to the interconnects used to wire the billions of transistors in next-generation microchips. You can see that each trench is partially filled with coppe... » read more

Interconnect Troubles

By Applied Materials Writers - 13 Dec, 2012 - Comments: 0

By Mehul Naik These days, transistor scaling is driving some of the most exciting innovations in device architecture and getting lots of attention as a result. What may be less obvious is the cascading effect transistor scaling is having on the interconnect. The biggest challenges result directly from pitch reduction required to support the increasing functionality. These include poor pattern ... » read more

Interconnect Performance In The Spotlight

By Applied Materials Writers - 04 Dec, 2012 - Comments: 0

By Richard Lewington Are you going to be in the San Francisco area on December 11th? We're hosting a forum to explore the path that interconnect technology must take to keep pace with transistor scaling and the transition to new 3D architectures. Transistors get all the attention these days as the savior of Moore's Law. But there's no point making transistors faster if the wires between ... » read more

Epitaxy: Seeking Crystalline Perfection

By Applied Materials Writers - 18 Oct, 2012 - Comments: 1

By Richard Lewington Epitaxy is one of the fundamental processes used to make all kinds of semiconductor devices: LEDs, power electronics and, of course, microchips. The term epitaxy means, roughly speaking, “adding order” and that’s exactly what it does. Hot gases react on a surface to “grow” a layer that precisely matches the underlying crystal structure. Epitaxy was first us... » read more

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Knowledge Centers
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