Speeding Up High-Frequency Trading

By Sunil Sahoo - 24 May, 2018 - Comments: 0

The High-Frequency Trading (HFT) industry has received a lot of attention during the last few years. HFT is all about speed and minimizing latency: the faster you can run trading strategies and algorithms for analyzing minute price changes and executing trade orders, the higher the probability to win over competition. So the competition in this area is very fierce with market players continuous... » read more

Inside UVM, Take Three

By Vatsal Choksi - 26 Apr, 2018 - Comments: 0

The reason why UVM came up with such phases is because synchronization among all design-testbench was necessary. Using Verilog and VHDL, verification engineers did not have facilities such as clocking block or run phases. Now, it is very important that the time at which test vectors applied from test-bench reaches the Design Under Test(DUT) at the same time. If timing for different signals vari... » read more

Simplifying SystemVerilog Functional Coverage

By Henry Chan - 22 Mar, 2018 - Comments: 0

Let’s say you have a block you need to verify. How do you know that the stimulus you are about to use is exhaustive enough and that you have covered the necessary scenarios/situations to prove it is working correctly? This is where functional coverage comes in. SystemVerilog’s functional coverage constructs allow you to quantify the completeness of your stimulus by recording the values that... » read more

Inside UVM, Take Two

By Vatsal Choksi - 22 Feb, 2018 - Comments: 0

In this blog, my major focus is on explaining the concepts such as Sequence, Sequencer, Driver and showing how the communication takes place from sequence to sequencer and from sequencer to driver. In the previous blog, I included a top-level diagram of the UVM structure, showing different base classes. So, let’s look at the main concepts and follow the communication mechanism they use for... » read more

Analyzing Data Differently

By Sunil Sahoo - 25 Jan, 2018 - Comments: 0

Data analysis is often a very time consuming process for a hardware design or verification engineer. We always end up using the waveform viewer which may not be very efficient in giving us a high-level overview of what we’re looking for. Data that is spread across a long simulation cycle is very hard to visualize on the waveform. Whenever I have to analyze a huge chunk of data, I always wonde... » read more

Partitioning With Ease

By Henry Chan - 21 Dec, 2017 - Comments: 0

Modern ASIC and SoC designs have increased in complexity such that multiple FPGAs of the largest capacity are now required to prototype the entire functionality of the design. As design sizes increase, more and more FPGAs are required. The capacity and pin limitations of FPGAs create constraints for how the ASIC/SoC design can be mapped into the FPGAs. Aldec’s HES-DVM's prototyping mode accou... » read more

Using FPGAs For Emulation

By Krzysztof Szczur - 30 Nov, 2017 - Comments: 0

For many years, emulators were available only to verification teams working on the largest projects in companies with deep enough pockets. Due to size rather than capabilities they were called “Big Box” emulators and typically were used in order to recover some of the time lost on RTL simulation. Meanwhile, FPGA technology has been available long enough to mature to the point where FPGA bas... » read more

Inside UVM

By Vatsal Choksi - 26 Oct, 2017 - Comments: 0

We have all been witnesses to the rapid improvements of the iPhone processor chip every year. With the iPhone 8 featuring the newest A11 Bionic at 10 nm FinFET with 4.3 billion transistors, I can’t personally fathom the amount of the verification effort needed for this type of SoC - the required manpower and time to get the job done is absolutely mind-boggling. Thankfully, we have several pre... » read more

Finite State Machine Synthesis In Programmable Circuits

By Radek Nawrot - 28 Sep, 2017 - Comments: 0

Well, summer has been and gone; and for most of us it was a time to relax and reflect on our working practices. What can we do to achieve better results? And what can we do to break out of the routine of working on so many revisions? For me, one of my summer break ponderings was thinking back on a trick I learned while working with my colleagues at the Silesian University of Technology. C... » read more

Traceability Matrices: Headache Or Real Value?

By Janusz Kitel - 24 Aug, 2017 - Comments: 0

Traceability is becoming increasingly important in most engineering projects, if only on the grounds of ‘good practice,’ and it is specifically required for projects that have to meet safety standards such as DO-254 and ISO 26262. To provide traceability, you must maintain the relationships between all aspects of a project; from the system-level requirements through implementation and ve... » read more

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