Optical Interconnectivity At 224 Gbps


AI is generating so much traffic that traditional copper-based approaches for moving data inside a chip, between chips, and between systems, are running out of steam. Just adding more channels is no longer viable. It requires more power to drive signals, and the distance those signals can travel without excessive loss is shrinking. Mike Klempa, product marketing specialist at Alphawave Semi, di... » read more

Problems In Testing AI Chips


As AI chips get larger, it becomes much harder to test them. Today, there can be as many as 22,000 pins on a 150mm² die, but in the future that number may increase to 80,000 pins. That creates a huge challenge for the fabs and the testers. Jack Lewis, chief technologist at Modus Test, talks about the intricacies of testing these complex devices, from maintaining contact with those pins even on... » read more

Speeding Up Die-To-Die Interconnectivity


Disaggregating SoCs, coupled with the need to process more data faster, is forcing engineering teams to rethink the electronic plumbing in a system. Wires don't shrink, and just cramming more wires or thicker wires into a package are not viable solutions. Kevin Donnelly, vice president of strategic marketing at Eliyan, talks about how to speed up data movement between chiplets with bi-direction... » read more

Conversing With Your Dishwasher


What does "Error 22" mean on your smart appliance? Today, most people have to look it up on the internet, but that's about to change. John Weil, vice president and general manager for Synaptics IoT and Edge AI Processor business unit, talks about how AI can be inexpensively and efficiently utilized by mapping directly to a database using a natural language interface. Unlike today, that informat... » read more

What’s Changing In SerDes


SerDes is all about pushing data through the smallest number of physical channels. But when it comes to AI, more data needs to be moved, and it has to be moved more quickly. Todd Bermensolo, product marketing manager at Alphawave Semi, talks about the impact of faster data movement on the transmitter (more power) and on the receiver (gain and advanced equalization), how to ensure signal inte... » read more

Optimizing Data Movement In SoCs And Advanced Packages


The amount of data that needs to move around a chip is growing exponentially, driven by the rollout of AI and more sensors everywhere. There may be hundreds of IP blocks, more compute elements, and many more wires to contend with. Andy Nightingale, vice president of product management and marketing at Arteris, talks about the demand for low-latency on-chip communication in increasingly complex ... » read more

Changes In Motor Control


Motors are changing in fundamental ways, and you can actually hear the difference. Vacuums, air conditioners, and home appliances are getting quieter. They're also becoming more efficient, able to last longer on a single battery charge or drawing less energy from the grid, and they're becoming more secure. Steve Tateosian, senior vice president for Infineon's IoT, Compute & Wireless Busines... » read more

What’s Changing In Outlier Detection


Commonly used outlier detection approaches, such as parts average testing or determining whether a die is good based upon other dies in the immediate neighborhood, are falling short in advanced packages and SoCs. Some devices may pass tests and still fail in the field. In the past, this was solved by adding margin into designs, but that margin now takes too big a bite out of performance and pow... » read more

Scenario Coverage In Formal Verification


A rapid increase in complexity with heterogeneous assemblies and advanced-node chips is raising all sorts of questions on the formal verification side about the completeness of coverage. Engineers may assume proofs are complete, but in many cases they're black boxes that provide little or no insights into what's actually being proven. This is where scenario coverage comes into play. Ashish Darb... » read more

Cracking The Memory Wall


Processor performance continues to improve exponentially, with more processor cores, parallel instructions, and specialized processing elements, but it is far outpacing improvements in bandwidth and memory. That gap, the so-called memory wall, has persisted throughout most of this century, but now it is becoming more pronounced. SRAM scaling is slowing at advanced nodes, which means SRAM takes ... » read more

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