Drew Wingard peels back the covers on dark silicon, the next big thing in semiconductors and what's needed to get there in a candid discussion with System-Level Design.
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Open-Silicon's CEO talks with System-Level Design about getting the business priorities of designing a complex SoC in line with the technology; why getting chips out the door on time is critical and why it's not happening.
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Bernard Murphy talks with System-Level Design about what's changing in the semiconductor design area, how 3D stacking will affect design and what's needed in EDA tools.
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eSilicon's CEO talks with System-Level Design about changes in design at advanced nodes, the power of 2.5D and 3D stacking, and how the semiconductor supply chain is changing.
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Mentor's Chairman and CEO sounds off about where the IC design challenges are, what needs to be done to fix them, and what new opportunities will unfold.
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System-Level Design talks with Mentor Graphics, Cadence, and an Accellera member about what's changing in verification--and where the missing pieces are.
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System-Level Design digs into the future of the design automation tools industry and the Design Automation Conference with Cadence's Neil Hand, Atrenta's Mike Gianfagna and Springsoft's Johnson Teng.
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System-Level Design talks with Bob Bluth of the Naval Postgraduate School about UAV design and debug challenges--and what's inside of these devices. (The blue and green cellophane tape seal some of the access points prior to delivery--and the directions).
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Gary Patton, VP at IBM's semiconductor R&D Center, talks with System-Level Design about the challenges of developing chips all the way down to 15nm.
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Simon Segars, ARM's executive vice president and general manager of the company's physical IP group, talks about the war with Intel and which markets it's likely to affect.
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AI export rule to be scrapped; SEMI, EU request; Cadence, Nvidia supercomputer; AI co-processor; Imagination's new GPU; semi sales up; imec, TNO photonics lab; NSF key to national security; flexible packaging control system; SiConic test engineering; USB 4 support; SiC JFETS; magnetic behavior in hematite.
AI cannot optimize unless it can measure progress towards goals, but defining those goals is not easy, especially when looking at the entire development flow.
AI export rule to be scrapped; SEMI, EU request; Cadence, Nvidia supercomputer; AI co-processor; Imagination's new GPU; semi sales up; imec, TNO photonics lab; NSF key to national security; flexible packaging control system; SiConic test engineering; USB 4 support; SiC JFETS; magnetic behavior in hematite.
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