Tech Talk: IP Integration


Sonics CTO Drew Wingard talks about the challenges of integrating IP into SoCs and what typically goes wrong. [youtube vid=T1FAPDqIJK8] » read more

Tech Talk: Photonics, Take 2


Mentor Graphics’ John Ferguson explains why light is getting so much attention for inter-chip communications, where it excels, and why it has limitations. This is the second part in a two-part series. [youtube vid=4-5FbxIpIk4] To view part 1, click here. » read more

Tech Talk: The New Cost Per Gate Equation


eSilicon's Javier DeLaCruz talks with Semiconductor Engineering about new types of interposers, why just shrinking features is doomed, and what progress has been made in building 2.5D chips. [youtube vid=akj8r8nNktM] » read more

Tech Talk: Silicon Photonics


Mentor Graphics' John Ferguson explains why light is getting so much attention for inter-chip communications, where it excels, and why it has limitations. This is the first part in a two-part series. [youtube vid=0ydkDmrSrF4] » read more

Tech Talk: Changes In Verification


Roger Hughes, director of strategic accounts at Real Intent, talks about what's changing in verification as design complexity increases and where engineers typically make mistakes. [youtube vid=0SE97LvCilo] » read more

Tech Talk: FPGA Prototyping


Neil Songcuan, senior product marketing manager at Synopsys, examines the hidden time savings from using an FPGA prototype platform for IP validation and software development, in addition to hardware design. While FPGA prototypes are a well known way of speeding up hardware design, their value in IP validation and software development for an integrated SoC is just beginning to surface. [you... » read more

Tech Talk: 2.5D Stacked Die


What's the motivation for moving to 2.5D packaging and architectures rather than following Moore's Law? Shafy Eltoukhy, VP of operations and technology development at Open-Silicon, talks with Semiconductor Engineering about adding another dimension in semiconductors. [youtube vid=HwpY9bUNt0w] » read more

New Pain And Inflection Points


Jack Harding, CEO of eSilicon, talks with Semiconductor Engineering about the explosion in the costs and the risk of semiconductor designs at the leading edge of Moore's Law. [youtube vid=HLS5QhnGHfM] » read more

Executive Briefing: Prakash Narain


Real Intent CEO Prakash Narain talks with System-Level Design about where are the pain points in verification; different types of signoff; the impact of third-party IP, and can the tools industry keep up with the rising complexity in semiconductor design. [youtube vid=C25VMRDXGAQ] » read more

Executive Briefing: Stacking The Odds


Open-Silicon CEO Naveed Sherwani talks with System-Level Design about progress on 2.5D and 3D stacked die, why this approach is inevitable, when it will begin and what markets will use it first. [youtube vid=mzwpgDKuIok] » read more

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