Finding Hardware Trojans

By Ed Sperling - 03 Dec, 2019 - Comments: 0

John Hallman, product manager for trust and security at OneSpin Technologies, looks at how to identify hardware Trojans in a design, why IP from different vendors makes this more complicated, and how a digital twin can provide a reference point against which to measure if a design has been compromised. » read more

Which Verification Engine When

By Ed Sperling - 31 Oct, 2019 - Comments: 0

Frank Schirrmeister, group director for product marketing at Cadence, talks about which tools get used throughout the design flow, from architecture to simulation, formal verification, emulation, prototyping all the way to production, how the cloud has impacted the direction of the flow, and how machine learning will impact verification. » read more

Visually Assisted Layout In Custom Design

By Ed Sperling - 29 Oct, 2019 - Comments: 0

Avina Verma, group director for R&D in Synopsys’ Design Group, explains why visual feedback and graphical guidance are so critical in complex layouts, particularly for mixed-signal environments. » read more

Signoff-Compatible CDC

By Ed Sperling - 29 Jul, 2019 - Comments: 2

Tanveer Singh, senior staff consulting applications engineer at Synopsys, explains why netlist clock domain crossing is now an essential complement to RTL CDC, why CDC issues are worse at advanced nodes and in AI chips, and why dealing with CDC effectively is becoming a competitive requirement for performance and low power. » read more

Verification In The Cloud

By Ed Sperling - 27 Jun, 2019 - Comments: 0

Christen Decoin, senior director of business development at Synopsys, talks with Semiconductor Engineering about what’s changed for EDA in the cloud, why it has taken so long, and what new benefits the cloud will offer. Rules have changed at foundries, and the customer base for designs is evolving. » read more

Analog Fault Simulation

By Ed Sperling - 30 May, 2019 - Comments: 0

Anand Thiruvengadam, senior staff product marketing manager at Synopsys, drills down into the need for fault simulation in analog circuits in automotive designs. » read more

Verification At 7/5nm

By Ed Sperling - 25 Apr, 2019 - Comments: 0

Christen Decoin, senior director of business development at Synopsys, talks about what’s missing in verification, how is that affected by complex chips such as 7nm SoCs or AI chips, and why more steps need to be done concurrently. https://youtu.be/bz6KyJh67sI » read more

Safety-Critical Coverage

By Ed Sperling - 24 Apr, 2019 - Comments: 0

Dave Landoll, solutions architect at OneSpin Solutions, discusses verification in safety-critical designs, why it’s more of a challenge in automotive than in avionics, and why verification of these systems includes what the system should not be doing as well as what it should be doing. https://youtu.be/Ze3WwEARfx0 » read more

Billion-Gate Design Connectivity

By Ed Sperling - 27 Mar, 2019 - Comments: 0

Sasa Stamenkovic, senior field application engineer at OneSpin Solutions, explains how to find and resolve connectivity issues in integrating large numbers of components in very big designs, often at the leading edge nodes and in markets such as AI. » read more

Debug Changes At Advanced Nodes

By Ed Sperling - 27 Mar, 2019 - Comments: 0

Ribhu Mittal, emulation applications director at Synopsys, zeroes in on what’s changing in debug, including why traditional verification methods are failing in designs with 1 billion gates and a commensurate amount of software complexity. The key is how to maintain or reduce time to market, and that requires a different way of approaching the problem. » read more

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Knowledge Centers
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