category: Videos

category: IoT, Security & Automotive

Context-Aware Debug
By Ed Sperling - 31 Jan, 2020 - Comments: 0

Moses Satyasekaran, product manager at Mentor, a Siemens Business, examines the growing complexity of debug, which now includes software, power intent and integration, multiple clocking and reset domains, and much more, where the limitations are for debug, and how automotive, functional safety and mixed signal affect the overall process. » read more

Analog Simulation At 7/5/3nm
By Ed Sperling - 27 Jan, 2020 - Comments: 0

Hany Elhak, group director of product management at Cadence, talks with Semiconductor Engineering about analog circuit simulation at advanced nodes, why process variation is an increasing problem, the impact of parasitics and finFET stacking, and what happens when gate-all-around FETs are added into the chip. » read more

Dealing With ECOs In Complex Designs
By Ed Sperling - 22 Jan, 2020 - Comments: 0

Namsuk Oh, R&D principal engineer at Synopsys, talks about the impact of more corners and engineering change orders, how that needs to be addressed in the flow to close timing, and how dependencies can complicate any changes that are required. » read more

Distributed Design Implementation
By Ed Sperling - 04 Dec, 2019 - Comments: 0

PV Srinivas, group director for R&D at Synopsys, talks about the impact of larger chips and increasing complexity on design productivity, why divide-and-conquer doesn’t work so well anymore, and how to reduce the number of blocks that need to be considered to achieve faster timing closure and quicker time to market. » read more

Finding Hardware Trojans
By Ed Sperling - 03 Dec, 2019 - Comments: 0

John Hallman, product manager for trust and security at OneSpin Technologies, looks at how to identify hardware Trojans in a design, why IP from different vendors makes this more complicated, and how a digital twin can provide a reference point against which to measure if a design has been compromised. » read more

Which Verification Engine When
By Ed Sperling - 31 Oct, 2019 - Comments: 0

Frank Schirrmeister, group director for product marketing at Cadence, talks about which tools get used throughout the design flow, from architecture to simulation, formal verification, emulation, prototyping all the way to production, how the cloud has impacted the direction of the flow, and how machine learning will impact verification. » read more

Visually Assisted Layout In Custom Design
By Ed Sperling - 29 Oct, 2019 - Comments: 0

Avina Verma, group director for R&D in Synopsys’ Design Group, explains why visual feedback and graphical guidance are so critical in complex layouts, particularly for mixed-signal environments. » read more

Signoff-Compatible CDC
By Ed Sperling - 29 Jul, 2019 - Comments: 2

Tanveer Singh, senior staff consulting applications engineer at Synopsys, explains why netlist clock domain crossing is now an essential complement to RTL CDC, why CDC issues are worse at advanced nodes and in AI chips, and why dealing with CDC effectively is becoming a competitive requirement for performance and low power. » read more

Verification In The Cloud
By Ed Sperling - 27 Jun, 2019 - Comments: 0

Christen Decoin, senior director of business development at Synopsys, talks with Semiconductor Engineering about what’s changed for EDA in the cloud, why it has taken so long, and what new benefits the cloud will offer. Rules have changed at foundries, and the customer base for designs is evolving. » read more

Analog Fault Simulation
By Ed Sperling - 30 May, 2019 - Comments: 0

Anand Thiruvengadam, senior staff product marketing manager at Synopsys, drills down into the need for fault simulation in analog circuits in automotive designs. » read more

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