Analog Simulation At 7/5/3nm

The impact of finFETs, parasitics and process variation on analog circuit design.


Hany Elhak, group director of product management at Cadence, talks with Semiconductor Engineering about analog circuit simulation at advanced nodes, why process variation is an increasing problem, the impact of parasitics and finFET stacking, and what happens when gate-all-around FETs are added into the chip.

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