Signoff Of Synthesis-Optimized Registers


How do you know when you sign off on a complex chip design that everything is going to work? There are more variables, more elements that need to be verified, and more waivers that need to be generated. Suresh Barla, senior director of field applications at Synopsys, talks about how to ensure that RTL is fully optimized for PPA targets in large designs that can include hundreds of millions of g... » read more

Building Multi-Agent Systems For ASIC Flows


If one AI agent can solve a problem in a certain amount of time, can multiple agents solve it faster? The answer is yes, but only if the agents have well-defined roles and targets. This is where orchestrators fit in, and why they are so critical to agentic AI. Kexun Zhang, head of research at ChipAgents, talks about what exactly AI agents are, how they can be used to solve big problems that wou... » read more

1 Megawatt Racks In Data Centers


The demand for performance in an AI data center is causing a huge spike in the amount of power being consumed. Within a rack are a half-dozen SoC components housed in different types of advanced packages and connected with an assortment of blazing-fast interface IP and optical signaling. Manmeet Walia, director of product management for mixed-signal PHY IP in the Synopsys Solutions Group, talks... » read more

The Evolution Of UCIe


Since it was released in March 2022, the Universal Chiplet Interconnect Express (UCIe) has grown from a basic way of connecting two dies together into a comprehensive specification that can ensure the handoff of data between various components in an advanced package, as well as validate the chiplets within that package. Mayank Bhatnagar, director of product marketing at Cadence, talks about the... » read more

Moving Defect Detection And Classification To The Edge


The number of defects detected through inspection is exploding at each new process node. There are now millions of defects being identified on each wafer, but only a fraction of those can cause problems. Prasad Bachiraju, senior director of business development at Onto Innovation, talks about the different types of images being captured using different illumination modes at different touch poin... » read more

Overcoming Bottlenecks In Data Movement


AI is all about data. There is more data to process, store, and move, and more tradeoffs required to do that efficiently and with enough flexibility to handle changes in future workloads. Nandan Nayampally, chief commercial officer at Baya Systems, talks about networks on chip and networks across chip, what the choke points are for data movement, and where and when data coherency makes sense. » read more

DFT In Automotive


Ensuring automotive chips are reliable, defect-free, and secure adds a whole new dimension to design for testability (DFT). Depending on the safety criticality of a system in an automobile, tests can range from key-on, once a car is started, to safety-critical features that may need to be tested every couple hundred milliseconds during operation. Lee Harrison, director of automotive IC solution... » read more

New CPU Memory Module


Moving data has become the top challenge inside data centers. There is more data to process, more to move, and more to store and retrieve from memory. This is where small outline compression attached memory modules (SOCAMMs) fit in. Frank Ferro, group director for product management at Cadence, talks about the benefits of this next-gen modular low-power memory standard, how it compares with oth... » read more

System-in-Package Challenges


Systems companies and leading-edge chipmakers are pushing past reticle limits with chiplet-based designs, often breaking compute-intensive functions into different chiplets and coupling those with other chiplets that may have been developed by different teams and at different process nodes. This is harder than it sounds, and results can vary widely even under the best circumstances. Nir Sever, ... » read more

Why Proof Convergence Matters


Achieving a deterministic "yes or no" answer in semiconductor verification is becoming more challenging as chip complexity increases. There are more cores, more potential interactions, and more reliance on AI to build AI chips. Ashish Darbari, CEO of Axiomise, talks about the impact of functional interactions involving safety and security, and where to look for common patterns to prevent bugs f... » read more

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