Tech Talk: Automotive Design

NetSpeed Systems CEO Sundari Mitra talks about how to speed up the design of automotive chips. » read more

Tech Talk: Faster Simulation

Cadence‚Äôs Adam Sherer talks about how to speed up simulation in complex multi-core designs. » read more

Tech Talk: On-Chip Variation

Raymond Nijssen, vice president of systems engineering at Achronix, discusses on-chip and process variation at 7nm and 5nm, the role of embedded FPGAs, and how to reduce margin and pessimistic designs. » read more

Tech Talk: eFPGA Density

Chen Wang, senior vice president of engineering at Flex Logix, talks about how to improve density in embedded FPGAs. » read more

Tech Talk: 5/3nm Parasitics

Ralph Iverson, principal R&D engineer at Synopsys, talks about parasitic extraction at 5/3nm and what to expect with new materials and gate structures such as gate-all-around FETs and vertical nanowire FETs. » read more

Tech Talk: Applying Machine Learning

Norman Chang, chief technologist at ANSYS, talks about real applications of machine learning for mechanical, fluid dynamics and chip-package-system design. » read more

Tech Talk: 5G

Mike Fitton, senior director of strategic planning at Achronix, talks about the new wireless standard, which will make its debut at the Winter Olympics, when it will go mainstream, and what kinds of technical issues need to be addressed to make that happen. » read more

Tech Talk: 7nm Process Variation

Ankur Gupta, director of field applications at ANSYS, discusses process variation and the problems it can cause at 10/7nm and beyond. » read more

Tech Talk: Debugging ASICs With Embedded FPGAs

Valy Ossman, senior architecture and applications engineer at Flex Logix, discusses the advantages of debugging an ASIC using an embedded FPGA, including time to market, flexibility in design, and after-market changes. » read more

Tech Talk: EM Crosstalk

Anand Raman, senior director at Helic, talks about the impact of electromagnetic interference on digital design at 10/7nm and beyond. Once confined to the analog space, noise is suddenly an issue at advanced nodes for all designs. At the root of the problem are smaller nodes, increased speed and higher levels of integration. » read more

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