2.5D, 3D Power Integrity


Chris Ortiz, principal applications engineer at ANSYS, zeroes in on some common issues that are showing up in 2.5D and 3D packaging, which were not obvious in the initial implementations of these packaging technologies. This includes everything from how to build a power delivery network to minimize the coupling between chips to dealing with variability and power integrity and placement of diffe... » read more

Designing An AI SoC


Susheel Tadikonda, vice president of networking and storage at Synopsys, looks at how to achieve economies of scale in AI chips and where the common elements are across all the different architectures. https://youtu.be/fm0kxnj3DuM » read more

The Winograd Transformation


Cheng Wang, senior vice president of engineering at Flex Logix, explains how the Winograd Transformation applies to convolutional neural networks. https://youtu.be/E7QJUby9x-I » read more

New Memory Options


Carlos Macián, eSilicon’s senior director of AI strategy and products, talks about how to utilize memory differently and reduce the movement of data in AI chips, and what impact that has on power and performance. https://youtu.be/wItp6wReVts » read more

Reverse Debug


Chun Chan, product applications engineering director at Synopsys, talks with Semiconductor Engineering about testbench debug and how adding time markers can speed time to signoff. https://youtu.be/tx_89M1bq3Q » read more

Designing Networking Chips


Susheel Tadikonda, vice president of networking and storage at Synopsys, talks about what’s changed in the way networking chips are being designed to deal with a massive increase in data. One of those shifts involves software-defined networking, where the greatest complexity resides in the software. That also has a big impact on the entire design flow, from pre-silicon to post-silicon. htt... » read more

Benchmarks For The Edge


Geoff Tate, CEO of Flex Logix, talks about benchmarking in edge devices, particularly for convolutional neural networks. https://youtu.be/-beVEpKAM4M » read more

Boosting Analog Reliability


Aveek Sarkar, vice president of Synopsys’ Custom Compiler Group, talks about challenges with complex design rules, rigid design methodologies, and the gap between pre-layout and post-layout simulation at finFET nodes. https://youtu.be/JRYlYJ31LLw » read more

Thermal Guard-Banding


Stephen Crosher, CEO of Moortec, talks with Semiconductor Engineering about the impact of more accurate measurements on power, performance and reliability of designs from 40nm all the way down to 3nm. https://youtu.be/VnX-TiaMVmI » read more

AI In Chip Manufacturing


Ira Leventhal, New Concept Product Initiative vice president at Advantest, talks with Semiconductor Engineering about using analysis and deep learning to make test more efficient and more effective. https://youtu.be/3VVG4JVnjHo » read more

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