category: Videos

category: Auto, Security & Edge AI

Verifying Networks On Chip
By Ed Sperling - 20 Jul, 2026 - Comments: 0

More data, more processing elements, and more memories are making it much harder to maintain consistent throughput in a multi-die assembly. There is more concurrent traffic, more potential interactions, and more protocol layers. Ashish Darbari, CEO of Axiomise, talks about the of coherency on serialization bugs, how to ensure data is secure, and how to ferret out the root cause of problems like... » read more

AI Models On The Edge
By Ed Sperling - 14 Jul, 2026 - Comments: 0

Moving from large language models in the cloud to small language models at the edge is much more complicated than just slimming down the algorithms. It requires changes in both hardware and software, and the constraints can vary greatly from one market segment to another. Daniel Firu, CPO and co-founder of Quadric, and Ravi Chakaravarthy, vice president of software at the company, talk about ho... » read more

How Far Left Can You Shift?
By Ed Sperling - 24 Jun, 2026 - Comments: 0

More steps in the design flow are shifting left, which makes a complicated design process even more complex. This includes early software prototyping, workload mapping, verification, multi-physics integration, verification, IP qualification. Frank Schirrmeister, executive director of strategic programs for System Solutions at Synopsys, talks about the increasing number of steps, the potential t... » read more

New USB Standards: Benefits And Incompatibilities
By Ed Sperling - 23 Jun, 2026 - Comments: 0

Just because it's a standard doesn't mean everything will work together, and this is especially evident with conflicting USB standards. David Shin, senior product marketing manager at Cadence Design Systems, explains where incompatibilities can crop up, why it's so difficult to control the different versions, and what's behind all this confusion. » read more

Will Your Chip’s Memory Work As Expected?
By Ed Sperling - 22 Jun, 2026 - Comments: 0

Increased density at advanced nodes, multi-die assemblies, and the rollout of AI everywhere are making it much more challenging to ensure that memory will function properly over its expected lifetime. Test is no longer about a single memory or one approach for testing memory. It can vary by application, by workload, and by architecture. Some testing is close to memory, some is built into memory... » read more

Signoff Of Synthesis-Optimized Registers
By Ed Sperling - 17 Jun, 2026 - Comments: 0

How do you know when you sign off on a complex chip design that everything is going to work? There are more variables, more elements that need to be verified, and more waivers that need to be generated. Suresh Barla, senior director of field applications at Synopsys, talks about how to ensure that RTL is fully optimized for PPA targets in large designs that can include hundreds of millions of g... » read more

Building Multi-Agent Systems For ASIC Flows
By Ed Sperling - 10 Jun, 2026 - Comments: 0

If one AI agent can solve a problem in a certain amount of time, can multiple agents solve it faster? The answer is yes, but only if the agents have well-defined roles and targets. This is where orchestrators fit in, and why they are so critical to agentic AI. Kexun Zhang, head of research at ChipAgents, talks about what exactly AI agents are, how they can be used to solve big problems that wou... » read more

1 Megawatt Racks In Data Centers
By Ed Sperling - 03 Jun, 2026 - Comments: 0

The demand for performance in an AI data center is causing a huge spike in the amount of power being consumed. Within a rack are a half-dozen SoC components housed in different types of advanced packages and connected with an assortment of blazing-fast interface IP and optical signaling. Manmeet Walia, director of product management for mixed-signal PHY IP in the Synopsys Solutions Group, talks... » read more

The Evolution Of UCIe
By Ed Sperling - 02 Jun, 2026 - Comments: 0

Since it was released in March 2022, the Universal Chiplet Interconnect Express (UCIe) has grown from a basic way of connecting two dies together into a comprehensive specification that can ensure the handoff of data between various components in an advanced package, as well as validate the chiplets within that package. Mayank Bhatnagar, director of product marketing at Cadence, talks about the... » read more

Moving Defect Detection And Classification To The Edge
By Ed Sperling - 29 May, 2026 - Comments: 0

The number of defects detected through inspection is exploding at each new process node. There are now millions of defects being identified on each wafer, but only a fraction of those can cause problems. Prasad Bachiraju, senior director of business development at Onto Innovation, talks about the different types of images being captured using different illumination modes at different touch poin... » read more

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