Yield Tracking In RDL


Yield is a much bigger issue when it comes to panel-level packages, which may contain up to 24 RDL layers. Just finding the defects is a massive challenge, let alone understanding how they will impact the entire device. Many of these advanced packages are being used in data centers for generative AI, and killer defects caused by bridges and opens can cause serious problems. What happens, for in... » read more

How To Stop Row Hammer Attacks


Row hammer is a well-publicized target for cyberattacks on DRAM, and there have been attempts to stop these attacks in DDR4 and DDR5, but with mixed results. The problem is that as density increases, distance decreases, making it more likely that flipped bit cell in one row can disturb a bit cell in another, and that bits flipped across an entire row can flip another row. Steven Woo, fellow and... » read more

What’s Changing In DRAM


More data requires more processing and more storage, because that data needs to be stored somewhere. What’s changing is that it’s no longer just about SRAM and DRAM. Today, multiple types of DRAM are used in the same devices, each with its own set of tradeoffs. C.S. Lin, marketing executive at Winbond, talks about the potential problems that causes, including mismatches in latency, and high... » read more

Reducing Power In Data Centers


The rollout of generative AI, coupled with more data in general, is requiring data centers to run servers harder and longer. That, in turn, is generating more heat and accelerating aging, and to ensure these systems continue working over their projected lifetimes, chipmakers are building extra margin into chips. That increases the amount of energy required to run and cool them, and it can short... » read more

Using Deep Data For Improved Reliability Testing


Reliability testing always has been a challenge for semiconductor companies, but it’s becoming much more difficult as devices continue to shrink, as they’re integrated together in advanced packages, and as they’re utilized under different conditions with life expectancy that varies by application and use case. Nir Sever, senior director of business development at proteanTecs, and Luca Mor... » read more

Densification Of RF Designs


It’s challenging enough to deal with wireless signals at the 5G and 6G frequencies. But with increased density in chips crammed into smaller packages, higher power, beam forming, and MIMO, design requirements are very different than in the past. Simple parasitic extraction no longer is sufficient. Daren McClearnon, product manager for RF and microwave simulation at Keysight, talks about the n... » read more

Very Short Reach SerDes In Data Centers


Speed is critical inside of data centers, and the distance that signals have to travel can have a big impact on time to results. But there are a number of variables that need to be considered, including what is an acceptable loss, how much power can be dissipated in a server rack, and what are the various connection options being used. Keivan Javadi Khasraghi, staff technical product manager at... » read more

Improving AI Productivity With AI


AI is showing up or proposed for nearly all aspects of chip design, but it also can be used to improve the performance of AI chips and to make engineers more productive earlier in the design process. Matt Graham, product management group director at Cadence, talks with Semiconductor Engineering about the role of AI in identifying patterns that are too complex for the human brain to grasp, how t... » read more

What To Do About Electrostatic Discharge


Electrostatic discharge is a well-understood phenomenon, but it’s becoming more difficult to plan for as single chips are replaced by multiple chips or chiplets in a package, and as the density of components continues to increase with each new node. In both cases, the probability for failure increases unless these sudden shocks are addressed in the design. Dermott Lynch, director of product m... » read more

Total Overlay With Multiple RDLs


As Advanced IC Substrates (AICS) add more RDL layers, requiring additional via connections between the RDL layers, the potential for cumulative overlay shift increases. This overlay shift can lead to longer RDL traces, which increases interconnect resistance, resulting in lower yield. Keith Best, director of product marketing, for lithography at Onto Innovation, talks about total overlay — th... » read more

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