Speeding Up FPGA Development


Salaheddin Hetalani, field application engineer at OneSpin Solutions, talks about why it’s getting harder to design and debug FPGAs, how much design time can be saved through formal techniques, and why just relying on programmability isn’t the most efficient approach. » read more

Hybrid Prototyping


David Svensson, applications engineer in Synopsys’ Verification Group, explains how a virtual transaction logic model can be connected to develop hardware-dependent drivers before RTL actually exists, why this is now critical for large, complex designs, and how to find the potential bottlenecks and debug both software and hardware. » read more

Why Is PSS So Important?


Robert Hoogenstryd, product marketing manager at Mentor, a Siemens Business, talks about the new testbench verification language standard, what are the big advantages of using PSS, what kinds of challenges this language solves, and how much time this approach can save. » read more

What’s In Your IP?


Jeff Markham, software architect at ClioSoft, talks with Semiconductor Engineering about IP traceability in markets such as automotive and aerospace, what’s actually in IP, what should not be in that IP from a security standpoint, and how all of this data can used to avert system reliability issues in the future. » read more

Understanding SLAM (Simultaneous Localization And Mapping)


Amol Borkar, senior product manager for AI and computer vision at Cadence, talks with Semiconductor Engineering about mapping and tracking the movement of an object in a scene, how to identify key corners in a frame, how probabilities of accuracy fit into the picture, how noise can affect that, and how to improve the performance and reduce power in these systems. » read more

EDA In The Cloud


Michael White, director of product marketing for Calibre physical verification at Mentor, a Siemens Business, looks at the growing compute requirements at 7, 5 and 3nm, why the cloud looks increasingly attractive from a security and capacity standpoint, and how the cloud as well as new lithography will affect the cost and complexity of developing new chips. » read more

Automotive Chip Design Workflow


Stewart Williams, senior technical marketing manager at Synopsys, talks about the consolidation of chips in a vehicle and the impact of 7/5nm on automotive SoC design, how to trade off power, performance, area and reliability, and how ISO 26262 impacts those variables. » read more

Reliability In Automotive Chips


Roland Jancke, head of department for design methodology at Fraunhofer IIS’ Engineering of Adaptive Systems Division, looks at how to ensure that chips used in cars are reliable over extended periods of use, how mission profiles vary depending upon where they are used, and why it’s important to understand what chips developed at the latest nodes can really be used for and how they will be ... » read more

Where Timing And Voltage Intersect


João Geada, chief technologist at ANSYS, talks about the limitations for power delivery networks and what processors can handle, why the current solutions to these issues are causing failures, and how voltage reduction can affect timing. » read more

Changes In AI SoCs


Kurt Shuler, vice president of marketing at ArterisIP, talks about the tradeoffs in AI SoCs, which range from power and performance to flexibility, depending on whether processing elements are highly specific or more general, and the need for more modeling of both hardware and software together. » read more

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