Techniques to predict failures and improve reliability.
At 7nm and 5nm, in-circuit monitoring is becoming essential. Steve Crosher, CEO of Moortec, talks about the impact of rising complexity, how different use cases and implementations can affect reliability and uptime, and why measuring electrical, voltage and thermal stress can be used to statistically predict failures and improve reliability throughout a chip’s lifetime.
While terms often are used interchangeably, they are very different technologies with different challenges.
The industry is gaining ground in understanding how aging affects reliability, but more variables make it harder to fix.
Key pivot and innovation points in semiconductor manufacturing.
Tools become more specific for Si/SiGe stacks, 3D NAND, and bonded wafer pairs.
Thinner photoresist layers, line roughness, and stochastic defects add new problems for the angstrom generation of chips.
Less precision equals lower power, but standards are required to make this work.
New applications require a deep understanding of the tradeoffs for different types of DRAM.
127 startups raise $2.6B; data center connectivity, quantum computing, and batteries draw big funding.
The industry is gaining ground in understanding how aging affects reliability, but more variables make it harder to fix.
Thermal mismatch in heterogeneous designs, different use cases, can impact everything from accelerated aging to warpage and system failures.
Technical and business challenges persist, but momentum is building.
The verification of a processor is a lot more complex than a comparably-sized ASIC, and RISC-V processors take this to another layer of complexity.
New memory standard adds significant benefits, but it’s still expensive and complicated to use. That could change.
As a reliability physicist, I found this conversation a bit disappointing. I would have liked to see what physical models and statistics are used to make the assessments of the full chip performance
Hi Jim, stay tuned for some follow-ups on that.