Techniques to predict failures and improve reliability.
At 7nm and 5nm, in-circuit monitoring is becoming essential. Steve Crosher, CEO of Moortec, talks about the impact of rising complexity, how different use cases and implementations can affect reliability and uptime, and why measuring electrical, voltage and thermal stress can be used to statistically predict failures and improve reliability throughout a chip’s lifetime.
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As a reliability physicist, I found this conversation a bit disappointing. I would have liked to see what physical models and statistics are used to make the assessments of the full chip performance
Hi Jim, stay tuned for some follow-ups on that.