category: Videos

category: IoT, Security & Automotive

Software In Inference Accelerators
By Ed Sperling - 10 Feb, 2020 - Comments: 0

Geoff Tate, CEO of Flex Logix, talks about the importance of hardware-software co-design for inference accelerators, how that affects performance and power, and what new approaches chipmakers are taking to bring AI chips to market. » read more

Ensuring Functional Safety In Design
By Ed Sperling - 05 Feb, 2020 - Comments: 0

Mohammed Abdelwahid (Ali), automotive logic test product manager at Mentor, a Siemens Business, discusses how to maximize coverage in the different ASIL standards for logic BiST, how to make testing more efficient, and what impact that has on area and test time. » read more

Ensuring Coverage In Large SoCs
By Ed Sperling - 04 Feb, 2020 - Comments: 0

Sven Beyer, product manager for design verification at OneSpin Solutions, talks about why formal technology is required to ensure coverage in some of the newest chips, how it deals with potential interactions and different use cases, and why it is gaining traction in automotive applications. » read more

Context-Aware Debug
By Ed Sperling - 31 Jan, 2020 - Comments: 0

Moses Satyasekaran, product manager at Mentor, a Siemens Business, examines the growing complexity of debug, which now includes software, power intent and integration, multiple clocking and reset domains, and much more, where the limitations are for debug, and how automotive, functional safety and mixed signal affect the overall process. » read more

Tradeoffs In Embedded Vision SoCs
By Ed Sperling - 28 Jan, 2020 - Comments: 0

Gordon Cooper, product marketing manager for embedded vision processors at Synopsys, talks with Semiconductor Engineering about the need for more performance in these devices, how that impacts power, and what can be done to optimize both prior to manufacturing. » read more

Analog Simulation At 7/5/3nm
By Ed Sperling - 27 Jan, 2020 - Comments: 0

Hany Elhak, group director of product management at Cadence, talks with Semiconductor Engineering about analog circuit simulation at advanced nodes, why process variation is an increasing problem, the impact of parasitics and finFET stacking, and what happens when gate-all-around FETs are added into the chip. » read more

Thermal Guardbanding
By Ed Sperling - 24 Jan, 2020 - Comments: 0

Stephen Crosher, CEO of Moortec, looks at the causes of thermal runaway in racks of servers and explains why accurate temperature measurement in AI and advanced-node chips is more critical, and what impact this has on performance when temperatures begin approaching acceptable limits. » read more

Dealing With ECOs In Complex Designs
By Ed Sperling - 22 Jan, 2020 - Comments: 0

Namsuk Oh, R&D principal engineer at Synopsys, talks about the impact of more corners and engineering change orders, how that needs to be addressed in the flow to close timing, and how dependencies can complicate any changes that are required. » read more

Network Storage Optimization In Chip Design
By Ed Sperling - 21 Jan, 2020 - Comments: 0

Prathna Sekar, technical account manager at ClioSoft, explains how to manage large quantities of data, how this can quickly spin out of control as colleagues check in data during the design process, and how to reduce the amount that needs to be stored. » read more

How Chips Age
By Ed Sperling - 20 Jan, 2020 - Comments: 1

Andre Lange, group manager for quality and reliability at Fraunhofer IIS’ Engineering of Adaptive Systems Division, talks about circuit aging, whether current methods of predicting reliability are accurate for chips developed at advanced process nodes, and where additional research is needed. » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2024 SMG   |  Terms of Service  |  Privacy Policy