What’s Changing In Outlier Detection


Commonly used outlier detection approaches, such as parts average testing or determining whether a die is good based upon other dies in the immediate neighborhood, are falling short in advanced packages and SoCs. Some devices may pass tests and still fail in the field. In the past, this was solved by adding margin into designs, but that margin now takes too big a bite out of performance and pow... » read more

Scenario Coverage In Formal Verification


A rapid increase in complexity with heterogeneous assemblies and advanced-node chips is raising all sorts of questions on the formal verification side about the completeness of coverage. Engineers may assume proofs are complete, but in many cases they're black boxes that provide little or no insights into what's actually being proven. This is where scenario coverage comes into play. Ashish Darb... » read more

Cracking The Memory Wall


Processor performance continues to improve exponentially, with more processor cores, parallel instructions, and specialized processing elements, but it is far outpacing improvements in bandwidth and memory. That gap, the so-called memory wall, has persisted throughout most of this century, but now it is becoming more pronounced. SRAM scaling is slowing at advanced nodes, which means SRAM takes ... » read more

Using AI In Semiconductor Inspection


AI is exceptionally good at spotting anomalies in semiconductor inspection. The challenge is training different models for different inspection tools and topographies, and knowing which model to use at any particular time. Different textures in backgrounds are difficult for traditional algorithms, for example. But once machine learning models are trained properly, they have proven effective in ... » read more

PCIe Over Optics


Moving data through a chip or package, and between packages and systems, is becoming a much bigger challenge as the volume of data continues to explode, and as more compute resources are deployed to work on data-intensive problems such as training AI algorithms or running long and complex simulations. There is more data to process in more places, more levels of data storage and access, and any ... » read more

The Road To Super Chips


Reticle size limitations are forcing chip design teams to look beyond a single SoC or processor in order to achieve orders of magnitude improvements in processing that are required for AI. But moving data between more processing elements adds a whole new set of challenges that need to be addressed at multiple levels. Steve Woo, distinguished inventor and fellow at Rambus, examines the benefits ... » read more

Livelocks And Deadlocks In NoCs


Devices that are stuck in a specific state, or which appear to be making progress even though they are not, are common problems in complex systems. Processing elements need to fetch data they don't have from routers may be frozen out by other processors, a problem that is exacerbated by common bus protocols. Ashish Darbari, CEO of Axiomise, talks about how to identify potential bottlenecks, why... » read more

Distributed Voltage And Frequency Scaling Gaining Traction


DVFS has been used in smart phones for more than a decade as a way of trading off power and performance when both are constrained, but much of the semiconductor industry has avoided this technique because it's too difficult to work with. That's starting to change as processing demands increase, driven by the rollout of AI everywhere and an increase in the number of features in advanced packages... » read more

Speeding Up Acoustic Wafer Inspection


Higher density and more vertical layers require higher-resolution inspection. In the past that generally resulted in longer scan times, which can slow throughput in the fab or assembly house. Bryan Schackmuth, senior product line manager at Nordson Test & Inspection, explains how rotational scanning using acoustic wafer inspection can speed up inspection time by a factor of eight, why it is... » read more

The Evolution of HBM


High-bandwidth memory originally was conceived as a way to increase capacity in memory attached to a 2.5D package. It has since become a staple for all high-performance computing, in some cases replacing SRAM for L3 cache. Archana Cheruliyil, senior product marketing manager at Alphawave Semi, talks about how and where HBM is used today, how it will be used in the future, why it is essential fo... » read more

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