New Challenges In Signoff


Multi-die assemblies coupled with leading-edge process nodes make signoff increasingly challenging and scary. There are more corner cases and more data to consider, but no slack in the delivery schedule. Marc Heyberger, product engineer group director at Cadence Design Systems, talks about full-chip timing, flat versus hierarchical timing analysis, the ongoing development of full 3D-ICs, and wh... » read more

New Performance Requirements For Audio


Demand for higher performance in audio is rising as human-machine interactions increase on the edge. That means more processing elements, and more challenges in keeping data consistent across those processors. Prakash Madhvapathy, director of product marketing and product management at Cadence, talks about the advantages of coherent designs, how that impacts security, and how DSPs are evolving ... » read more

Wi-Fi 7 Moves To The IoT


Wi-Fi 7 has been a staple in high-end applications such as notebook computers and AR/VR glasses for the past couple years, where high-speed connectivity and low latency are essential. Known alternatively as IEEE 802.11be, and Extremely High Throughput Wi-Fi, it is starting to migrate downstream into IoT devices such as smart door locks, thermostats, and robotic vacuum cleaners. But the reason i... » read more

Changes In Chip Architectures At The Edge


Edge computing is all about low latency, within a tight power budget, and with sufficient performance. This is very different from an AI data center, where the real focus is on data throughput between processor and memory. Achieving those goals requires a focus on what different processing elements bring to the table. Nigel Drego, co-founder and CTO of Quadric, talks about how these different c... » read more

Agentic AI In Chip Manufacturing


Agentic AI — breaking AI into individual agents that can work together and collaboratively — will be the real game changer for AI in chip manufacturing. By taking humans out of the loop, these agents can be programmed using natural language to automatically solve problems and improve efficiency. Jon Herlocker, vice president and general manager of software analytics at Cohu, talks  about w... » read more

Software-Defined Systems


Using high-level software languages to define semiconductors is faster, easier, and allows for more changes long before the RTL stage. This is especially useful for chiplets and embedded accelerators, which are narrower in scope and more targeted at different workloads and specific domains. But there are some caveats for engineers working in this space. Russell Klein, program director for Sieme... » read more

Challenges In Moving Data In Chips


The number of processes running simultaneously inside of chips is growing, fueled by massive increases in data from AI and sensors everywhere. The challenge now, particularly in multi-die assemblies, is how to prioritize where signals go, how quickly they move, and when they're supposed to arrive at shared memories. Andy Nightingale, vice president of product management and marketing at Arteris... » read more

Reliability And Traceability In Advanced Packages


The move from planar SoCs to advanced packages can improve performance and provide flexibility in large designs, which are difficult to fit onto a single reticle-sized die. But ensuring the device works as expected remains a challenge. There are multiple packaging options to choose from — 2.5D, fan-out wafer-level packaging, 3D-ICs, and various types of system-in-package — and many possible... » read more

Generative AI In Chip Manufacturing


Generative AI is a natural-language or text-based query, predicting patterns based on a massive set of data. While most of the attention has been focused on chatbots and copilots, it also can be used to identify small, transient aberrations in semiconductor manufacturing that are otherwise difficult to find. Jon Herlocker, vice president and general manager of software analytics at Cohu, talks ... » read more

DFT Shifts Further Left


Design for test is now an essential part of all advanced-node designs, but DFT dynamics are changing with the move to multi-die assemblies. More components, including chiplets, make it imperative to analyze more data earlier. Jeff Meyer, product manager for Tessent logic test at Siemens EDA, talks about how to reduce the cost of this analysis and the time it takes to do it, how much can be shif... » read more

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