category: Videos

category: IoT, Security & Automotive

Challenges Of Testing Advanced Packages
By Ed Sperling - 19 Sep, 2023 - Comments: 0

The number of things that can wrong in assembly and test increases as more chips are added into a package. Testing is the usual guarantor of a reliable device, but in an advanced package there are all sorts of new issues — more contacts, different handling requirements, the necessary thermal conditions for test, and variation within the package. George Harris, vice president of global test se... » read more

Challenges In Ramping New Manufacturing Processes
By Ed Sperling - 30 Aug, 2023 - Comments: 0

Despite a slowdown for Moore’s Law, there are more new manufacturing processes rolling out faster than ever before. The challenge now is to decrease time to yield, which involves everything from TCAD and design technology co-optimization, to refinement of power, performance, area/cost, and process control and analytics. Srinivas Raghvendra, vice president of engineering at Synopsys, talks abo... » read more

Manual X-ray Inspection
By Ed Sperling - 28 Aug, 2023 - Comments: 0

Increased density in advanced node chips and advanced packaging offers a way to greatly improve performance and reduce power, but it also makes it harder to inspect these devices for real and latent defects. Higher density can lead to scattering of light, and heterogeneous integration in a package means it’s not always possible to see through all materials equally. Chris Rand, product line ma... » read more

Speeding Up Design Closure
By Ed Sperling - 23 Aug, 2023 - Comments: 0

Increasing complexity and smaller process nodes make it far more difficult to achieve design closure for chips. There are more physical effects to model, including noise, cross-talk, and double switching effects, all of which can slow the design process. Solaiman Rahim, vice president of engineering for Synopsys’ EDA Group, talks about why it’s so important to analyze violations in design, ... » read more

High-NA EUV Progress And Problems
By Gregory Haley - 22 Aug, 2023 - Comments: 0

High-NA EUV will enable logic scaling for at least the next couple process nodes. It’s complex, expensive, and a feat of optical engineering, but there are a lot of components with mixed progress. Harry Levinson, principal lithographer at HJL Lithography, talks  about when this technology will likely show up, what problems still need to be resolved, and what comes next. Related Readin... » read more

Tradeoffs In DSP Design
By Ed Sperling - 07 Aug, 2023 - Comments: 0

More intelligence is now required in the front-, mid-, and back-haul for 5G/6G communication, requiring a mix of high performance, low power, and enough flexibility to accommodate constantly changing protocols and algorithms. One solution to these conflicting goals involves reconfigurable DSPs, in which the processing element is hardwired like an ASIC but still configurable for a variety of app... » read more

New Approaches To Sensors And Sensing
By Ed Sperling - 02 Aug, 2023 - Comments: 0

Sensors are becoming more intelligent, more complex, and much more useful. They are being integrated with other sensors in sensor fusion, so a smart doorbell may only wake up when it’s imperative to see who’s at the door, and a microphone may only send alerts when there are cries for help or sounds of glass breaking. Kim Lee, senior director of system applications engineering at Infineon, t... » read more

Using AI To Close Coverage Gaps
By Ed Sperling - 26 Jul, 2023 - Comments: 0

Verification of complex, heterogeneous chips is becoming much more difficult and time-consuming. There are more corner cases, and devices have to last longer and behave according to spec throughout their lifetimes. This is where AI fits in. It can help identify redundancy and provide information about why a particular device or block may not be able to be fully covered, and it can do it in less... » read more

RTL Restructuring Issues
By Ed Sperling - 18 Jul, 2023 - Comments: 0

Modification of modules in RTL is the last place in chip design where changes can be made relatively easily before they reach physical design, but it’s still as complicated as the design itself — and it becomes more difficult in 3D-ICs. Jim Schultz, product marketing manager for digital design implementation at Synopsys, talks about grouping and ungrouping, re-parenting, and breaking connec... » read more

Megatrends At DAC
By Ann Mutschler - 17 Jul, 2023 - Comments: 0

Spotting key trends over three days of a semiconductor design conference is a challenge, but some important ones come into focus after attending multiple sessions — AI/ML, chiplet integration, and heterogeneous integration in an SoC and package. Frank Schirrmeister, vice president solutions and business development at Arteris IP, talks about a variety of topics that fit under the DAC umbrella... » read more

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