category: Videos

category: Auto, Security & Edge AI

LPDDR6: Not Just For Mobile Anymore
By Ed Sperling - 03 Nov, 2025 - Comments: 0

LPDDR memory has been almost synonymous with mobile devices, but starting with the new LPDDR6 specification released in July 2025 by JEDEC, it will begin showing up inside of data centers, as well, early next year. The key factors in various flavors of DRAM are bandwidth, capacity, and cost. HBM is the fastest, but it's also expensive, and it requires a 2.5D or 3.5D packaging approach. GDDR is ... » read more

Critical Factors For Storing Data In DRAM
By Ed Sperling - 27 Oct, 2025 - Comments: 0

DRAM is becoming more complicated to develop, and more difficult to manage inside AI data centers. In the past, latency, bandwidth, and capacity were the primary considerations. But as the amount of data that needs to be processed, moved, and stored continues to rise, a whole new set of factors is emerging. Steven Woo, fellow and distinguished inventor at Rambus, talks about latency under load,... » read more

In-System Test For AI Data Centers
By Ed Sperling - 20 Oct, 2025 - Comments: 0

Testing inside the fab or packaging house can determine whether a chip or package meets all the functional requirements at time zero, but how that chip behaves in the field during its lifetime and under different workloads and environmental conditions may be very different. This is particularly true in AI data centers, where utilization of one or more dies may be significantly higher than in pr... » read more

Using AI/ML To Find And Correlate IC Test Data
By Ed Sperling - 15 Oct, 2025 - Comments: 0

What causes low yield in wafers? Usually it's due to design or process changes, but sometimes yield issues occur even if there haven't been any changes from one manufacturing lot to the next. Finding the cause requires some sleuthing, and the best approach for pinpointing problems is to mine design, process, and manufacturing data, and to correlate that data by date and time, by which equipment... » read more

Multi-Die Verification
By Ed Sperling - 13 Oct, 2025 - Comments: 1

Chiplets offer unprecedented flexibility in high-performance designs, but they also add new challenges on the verification side. Changing out a chiplet, or adding a new one, can mean having to re-verify an entire multi-die system, a problem that becomes even more complicated if those chiplets are developed by different vendors. Paul Graykowski, director of product marketing at Cadence Design Sy... » read more

The Rise Of AI Co-Processors
By Ed Sperling - 29 Sep, 2025 - Comments: 0

Figuring out the best kinds of processors to use for different AI workloads is a challenge. AI algorithms are undergoing rapid and frequent changes, and the workloads tied to them can vary by data type, by user, and sometimes because of software/firmware updates. On top of that, AI computations tend to require much higher utilization rates than traditional computing, and that will only become m... » read more

Benefits And Challenges Of Using Chiplets
By Ed Sperling - 24 Sep, 2025 - Comments: 0

The move to chiplets opens the door to more features than can be packed into a reticle-sized SoC. That potentially means more processing power, simpler designs, and higher yields. But it's not as simple as swapping LEGO blocks into a chassis. Ashley Stevens, director of product management and marketing at Arteris, talks with Semiconductor Engineering about the challenges of using coherent versu... » read more

Silicon Lifecycle Management
By Ed Sperling - 22 Sep, 2025 - Comments: 0

How chips are used is changing, and so are the requirements. In the past, markets were largely segmented by application, which determined how chips were designed. High-performance processors went into notebook computers, low-power chipsets were deployed in mobile devices, and complex SoCs and advanced packages were used in data centers. But with the spread of AI everywhere, traditional segmenta... » read more

Virtual Metrology In Semiconductor Manufacturing
By Ed Sperling - 19 Sep, 2025 - Comments: 0

Fourth in a seven-part series: Virtual metrology may never be 100% perfect because of the almost unlimited number of changes in a fab tools and the unique chip and wafer designs they're being used to process. But there are places where virtual metrology does make sense. Jon Herlocker, vice president and general manager of software analytics at Cohu, talks about why virtual metrology will never ... » read more

Virtual Twins: Layers Of Challenges
By Ed Sperling - 15 Sep, 2025 - Comments: 0

Virtual twins can provide deep insights into complex systems at any point in time, but creating them requires integrating a stack of abstractions that don't naturally go together. One abstraction may be mechanical, another electrical, and the data used to create those abstraction layers needs to be fused together logically and updated over time. David Fried, corporate vice president at Lam Rese... » read more

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