Tradeoffs In Embedded Vision SoCs

By Ed Sperling - 28 Jan, 2020 - Comments: 0

Gordon Cooper, product marketing manager for embedded vision processors at Synopsys, talks with Semiconductor Engineering about the need for more performance in these devices, how that impacts power, and what can be done to optimize both prior to manufacturing. » read more

Analog Simulation At 7/5/3nm

By Ed Sperling - 27 Jan, 2020 - Comments: 0

Hany Elhak, group director of product management at Cadence, talks with Semiconductor Engineering about analog circuit simulation at advanced nodes, why process variation is an increasing problem, the impact of parasitics and finFET stacking, and what happens when gate-all-around FETs are added into the chip. » read more

Thermal Guardbanding

By Ed Sperling - 24 Jan, 2020 - Comments: 0

Stephen Crosher, CEO of Moortec, looks at the causes of thermal runaway in racks of servers and explains why accurate temperature measurement in AI and advanced-node chips is more critical, and what impact this has on performance when temperatures begin approaching acceptable limits. » read more

Dealing With ECOs In Complex Designs

By Ed Sperling - 22 Jan, 2020 - Comments: 0

Namsuk Oh, R&D principal engineer at Synopsys, talks about the impact of more corners and engineering change orders, how that needs to be addressed in the flow to close timing, and how dependencies can complicate any changes that are required. » read more

Network Storage Optimization In Chip Design

By Ed Sperling - 21 Jan, 2020 - Comments: 0

Prathna Sekar, technical account manager at ClioSoft, explains how to manage large quantities of data, how this can quickly spin out of control as colleagues check in data during the design process, and how to reduce the amount that needs to be stored. » read more

How Chips Age

By Ed Sperling - 20 Jan, 2020 - Comments: 1

Andre Lange, group manager for quality and reliability at Fraunhofer IIS’ Engineering of Adaptive Systems Division, talks about circuit aging, whether current methods of predicting reliability are accurate for chips developed at advanced process nodes, and where additional research is needed. » read more

Using Static Analysis For Functional Safety

By Ed Sperling - 15 Jan, 2020 - Comments: 0

Fadi Maamari, group director for R&D at Synopsys, explains why static analysis is suddenly in demand in auto chip design, how it can help to choose the best implementation of functional safety approaches, and where it fits into the design flow. » read more

3 Safety Standards For Auto Electronics

By Ed Sperling - 13 Jan, 2020 - Comments: 0

Kurt Shuler, vice president of marketing at Arteris IP, drills down into the three main safety standards, ISO 26262, SOTIF (Safety of the Intended Function) and UL 4600, what each one covers, what the intent is behind them, and what this means for companies developing technology for future vehicles. » read more

Bridging Math And Engineering In ML

By Ed Sperling - 08 Jan, 2020 - Comments: 0

Steve Roddy, vice president of products for Arm’s Machine Learning Group, examines the intersection of high-level mathematics in the data science used in machine learning within area, speed, and power limitations, and how to bring these two worlds together with the least amount of disruption. » read more

Scan Diagnosis

By Ed Sperling - 20 Dec, 2019 - Comments: 1

Jayant D’Souza, product manager at Mentor, a Siemens Business, explains the difference between scan test and scan diagnosis, what causes values in a scan test to change, how this can be used to hone in on the actual cause of a failure in a design, and how to utilize test hardware more efficiently. » read more

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category: Videos

category: IoT, Security & Automotive

Tradeoffs In Embedded Vision SoCs

Analog Simulation At 7/5/3nm

Thermal Guardbanding

Dealing With ECOs In Complex Designs

Network Storage Optimization In Chip Design

How Chips Age

Using Static Analysis For Functional Safety

3 Safety Standards For Auto Electronics

Bridging Math And Engineering In ML

Scan Diagnosis

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