Variability In Chip Manufacturing


Brewer Science’s Jim Korich talks about how to deal with variability in processes and why consistency in materials is so important at advanced nodes. https://youtu.be/U1KkUmtmqpE » read more

The Next Big Chip Companies


Rambus’ Mike Noonen looks at why putting everything on a single die no longer works, what comes after Moore’s Law, and what the new business model looks like for chipmakers. https://youtu.be/X6Kca8Vm-wA » read more

eFPGA vs. FPGA Design Methodologies


Namit Varma, senior director of Achronix’s India Technology Center, discusses the differences between discrete and embedded FPGAs. https://youtu.be/Vwo3ktQvcKc » read more

Using High-Bandwidth Memory


eSilicon’s Tim Horel talks about HBM, what engineers need to know to work with this technology, and how it integrates with ASICs at advanced nodes. https://youtu.be/0Yq2XHGF6UE » read more

Planning Out Verification


OneSpin Solutions’ Nicolae Tusinschi talks with Semiconductor Engineering about how to move from specification to signoff in a verification flow. https://youtu.be/2zrgaq2I1SQ » read more

Thermal Impact On Reliability At 7/5nm


Haroon Chaudhri, director of RedHawk Analysis Fusion at Synopsys, talks about why thermal analysis is shifting left in the design cycle and why this is so critical at the most advanced process nodes. https://youtu.be/wjkrEFLb2vY » read more

Hybrid Memory


Gary Bronner, senior vice president of Rambus Labs, talks about the future of DRAM scaling, why one type of memory won’t solve all needs, and what the pros and cons are of different memories. https://youtu.be/R0hhDx2Fb7Q » read more

Huge Performance Gains Ahead


Rambus Chief Scientist Craig Hampel talks about what will drive the next big performance gains after Moore’s Law, from the data center to the edge. https://youtu.be/ItHCsei7YTc » read more

Energy-Efficient AI


Carlos Maciàn, senior director of innovation for eSilicon EMEA, talks about how to improve the efficiency of AI operations by focusing on the individual operations, including data transport, computation and memory. https://youtu.be/A3p_w7ENefs » read more

UPF-Aware Clock-Domain Crossing


Synopsys’ Namit Gupta talks with Semiconductor Engineering about low-power design techniques at the most advanced process nodes, including how to verify the impact of CDC on power at the register transfer level, how to avoid bugs caused by the post-RTL insertion of low-power devices such as isolation, retention and level shifters. https://youtu.be/HwRe9DHLfmg » read more

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