Manufacturing Ecosystem Challenges

By Ed Sperling - 19 Jun, 2013 - Comments: 0

What are the challenges facing semiconductor manufacturers and designers at the leading edge of Moore's Law? Semiconductor Manufacturing & Design asked Kevin Kranen of Synopsys, Seow Yin Lim of Cadence, Michael Buehler-Garcia of Mentor Graphics and Tom Quan of TSMC. [youtube vid=d6-zMJSxnpg] » read more

Executive Briefing: Formal Attire

By Ed Sperling - 06 Jun, 2013 - Comments: 0

Kathryn Kranen, CEO of Jasper Design Automation, talks with Low Power-High-Performance Engineering about formal verification, where the pain points are in SoC design, and why there is still life left in Moore's Law. [youtube vid=x4jlo6_RRqw] » read more

Tech Talk: FinFETs, FD-SOI And The Future Of SoC Design

By Ed Sperling - 04 Jun, 2013 - Comments: 0

Mary Ann White, marketing manager for Synopsys' Galaxy Implementation Platform, talks with Low-Power/High-Performance Engineering about new opportunities to reduce power and improve performance, and where the pain points will be. [youtube vid=kuJdcHIRxfU] » read more

RTL Signoff

By Ed Sperling - 03 Jun, 2013 - Comments: 0

Piyush Sancheti, Atrenta's vice president of product marketing, talks with Low-Power/High-Performance Engineering about where the pain points are in design and why RTL signoff has become so important. [youtube vid=8Ra1_VmzW50] » read more

Executive Briefing: Stacking The Odds

By Ed Sperling - 29 May, 2013 - Comments: 0

Open-Silicon CEO Naveed Sherwani talks with System-Level Design about progress on 2.5D and 3D stacked die, why this approach is inevitable, when it will begin and what markets will use it first. [youtube vid=mzwpgDKuIok] » read more

IP Play

By Ed Sperling - 29 May, 2013 - Comments: 0

Cadence Senior Vice President Martin Lund talks about the future of IP, why his company has been on an IP acquisition binge, and the new focus on mass-customization. [youtube vid=FdmBIlXpGVk] » read more

FinFETs On SOI

By Ed Sperling - 13 May, 2013 - Comments: 0

Soitec's Steve Longoria talks with Semiconductor Manufacturing and Design about what's changing at the leading edge of Moore's Law and why those changes are necessary. [youtube vid=K6D39QqJWSU] » read more

Roundtable: Is The Chip Ready

By Ed Sperling - 09 May, 2013 - Comments: 0

Mobile devices demand complex chips—so complex to build that signoff has become something of a balancing act between what the verification teams believe is good enough and time-to market demands. Low-Power/High-Performance Engineering talked about this with Simbal Rafiq, director of engineering at Applied Micro; Robert Hoogenstryd, senior director of marketing for design analysis and signoff ... » read more

Verifying Complex Chips

By Ed Sperling - 27 Feb, 2013 - Comments: 0

System-Level Design talks about what's changing in SoC verification with Janick Bergeron, verification fellow at Synopsys; Harry Foster, chief verification scientist at Mentor Graphics; Pranav Ashar, chief technology officer at Real Intent; Raik Brinkmann, president and CEO of OneSpin Solutions, and Tom Anderson, vice president of marketing at Breker Verification Systems. [youtube vid=DzDYyf... » read more

FinFETs, EUV And Moore’s Law

By Ed Sperling - 21 Feb, 2013 - Comments: 0

GlobalFoundries VP Subramani Kengeri talks about progress and problems with advanced processes with Semiconductor Manufacturing & Design. [youtube vid=_Ang0I1vWdI] » read more

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category: Videos

category: IoT, Security & Automotive

Manufacturing Ecosystem Challenges

Executive Briefing: Formal Attire

Tech Talk: FinFETs, FD-SOI And The Future Of SoC Design

RTL Signoff

Executive Briefing: Stacking The Odds

IP Play

FinFETs On SOI

Roundtable: Is The Chip Ready

Verifying Complex Chips

FinFETs, EUV And Moore’s Law

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