Low-Power Verification


Low-Power Engineering talks about how to verify the power portion of semiconductor designs with Krishna Balachandran of Synopsys; Barry Pangrle of Mentor Graphics; Kalar Rajendiran of eSilicon; Will Ruby of Apache Design, and Lauro Rizzatti of Eve-USA. [youtube vid=covy6ku6RgA] » read more

Roundtable: What’s Changing In System-Level Design


System-Level Design talks about what's changing and what's needed with Juan Rey of Mentor Graphics: Yervant Zorian of Synopsys; Michael McNamara of Cadence; Prasad Subramaniam of eSilicon; and Ravi Varadarajan of Atrenta. [youtube vid=8siiKBKD0-k] » read more

Making Software Better


Low-Power Engineering talks about what will make software more energy-efficient with Pete Hardee, marketing director at Cadence; Adam Kaiser, Nucleus RTOS architect at Mentor Graphics; Chris Rowen, CTO of Tensilica; Vic Kulkarni, senior VP and General Manager of Apache Design, and Bill Neifert, CTO of Carbon Design. [youtube vid=Jxquj8K8_BA] » read more

Tech Talk: Comparing Smart Phones


What makes one smart phone last longer on a charge than another? The answer may surprise you. Low-Power Engineering talks with Cary Chin, director of technical marketing for low-power solutions at Synopsys, about what his months of research have shown. [youtube vid=BUefmd_oFp8] » read more

Executive Briefing: The End Of CMOS?


Steve Longoria, senior vice president of Soitec, talks with System-Level Design about why silicon on insulator has suddenly become essential to semiconductor manufacturing and what it will mean for Moore's Law. [youtube vid=kNl1RSEpqKc] » read more

Time For FD-SOI?


Paul Boudre, COO of Soitec, talks with Semiconductor Manufacturing & Design about why SOI has suddenly become so interesting in semiconductor manufacturing and how it will affect the move to FinFETs. [youtube vid=DO9zfrinbOg] » read more

Using High-Level Synthesis To Manage Power


Low-Power Engineering talks with Apache Design's Vic Kulkarni, Tensilica's Grant Martin, Cadence's Mike Meyer, Calypto's Shawn McCloud and Forte Design's Brett Cline about the need for a higher level of abstraction to optimize power in ICs. [youtube vid=gpWacAhMYgo] » read more

Executive Briefing: 3D IC Stacking Challenges


Sonics CEO Grant Pierce sounds off on the challenges of stacking die, what has to change and why. [youtube vid=wCseVs738LQ] » read more

Tech Talk: Graphic Headaches


Nvidia senior vice president of GPU engineering Jonah Alben talks with System-Level Design about the challenges of designing a graphics chip at advanced process nodes. [youtube vid=3Nc77aVH94g] » read more

The Challenge of 3D


Juan Rey, senior director of engineering for Mentor Graphics' Design To Silicon Division, talks about 3D stacking and 3D structures on chips. [youtube vid=YiH5IkxiEHU] » read more

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