Tech Talk: 2.5D Stacked Die


What's the motivation for moving to 2.5D packaging and architectures rather than following Moore's Law? Shafy Eltoukhy, VP of operations and technology development at Open-Silicon, talks with Semiconductor Engineering about adding another dimension in semiconductors. [youtube vid=HwpY9bUNt0w] » read more

Tech Talk: 16nm-14nm Effects And Challenges


Arvind Shanmugavel from Apache Design talks with Semiconductor Engineering about electromigration, electrostatic discharge and thermal effects caused by increasing power density in finFETs.   [youtube vid=GOra5uYyIr8] » read more

New Pain And Inflection Points


Jack Harding, CEO of eSilicon, talks with Semiconductor Engineering about the explosion in the costs and the risk of semiconductor designs at the leading edge of Moore's Law. [youtube vid=HLS5QhnGHfM] » read more

Expert on Expert: The Higgs Boson


Mentor Graphics CEO Wally Rhines, a materials scientist, talks with Dr. Sean Carroll, a particle physicist at the California Institute of Technology about the discovery of the Higgs Boson, the cost of future discoveries, and what's left for physicists to discover. [youtube vid=qokwittw_8k] » read more

Executive Briefing: Prakash Narain


Real Intent CEO Prakash Narain talks with System-Level Design about where are the pain points in verification; different types of signoff; the impact of third-party IP, and can the tools industry keep up with the rising complexity in semiconductor design. [youtube vid=C25VMRDXGAQ] » read more

Foundry Talk


GlobalFoundries CEO Ajit Manocha sounds off on Foundry 2.0, 450mm wafers, lithography challenges, stacked die, the Internet of Things and the rush to the next process node. [youtube vid=WfjtlZkCi0w] » read more

Manufacturing Ecosystem Challenges


What are the challenges facing semiconductor manufacturers and designers at the leading edge of Moore's Law? Semiconductor Manufacturing & Design asked Kevin Kranen of Synopsys, Seow Yin Lim of Cadence, Michael Buehler-Garcia of Mentor Graphics and Tom Quan of TSMC. [youtube vid=d6-zMJSxnpg] » read more

Executive Briefing: Formal Attire


Kathryn Kranen, CEO of Jasper Design Automation, talks with Low Power-High-Performance Engineering about formal verification, where the pain points are in SoC design, and why there is still life left in Moore's Law. [youtube vid=x4jlo6_RRqw] » read more

Tech Talk: FinFETs, FD-SOI And The Future Of SoC Design


Mary Ann White, marketing manager for Synopsys' Galaxy Implementation Platform, talks with Low-Power/High-Performance Engineering about new opportunities to reduce power and improve performance, and where the pain points will be. [youtube vid=kuJdcHIRxfU] » read more

RTL Signoff


Piyush Sancheti, Atrenta's vice president of product marketing, talks with Low-Power/High-Performance Engineering about where the pain points are in design and why RTL signoff has become so important. [youtube vid=8Ra1_VmzW50] » read more

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