Executive Briefing: Stacking The Odds


Open-Silicon CEO Naveed Sherwani talks with System-Level Design about progress on 2.5D and 3D stacked die, why this approach is inevitable, when it will begin and what markets will use it first. [youtube vid=mzwpgDKuIok] » read more

IP Play


Cadence Senior Vice President Martin Lund talks about the future of IP, why his company has been on an IP acquisition binge, and the new focus on mass-customization. [youtube vid=FdmBIlXpGVk] » read more

FinFETs On SOI


Soitec's Steve Longoria talks with Semiconductor Manufacturing and Design about what's changing at the leading edge of Moore's Law and why those changes are necessary. [youtube vid=K6D39QqJWSU] » read more

Roundtable: Is The Chip Ready


Mobile devices demand complex chips—so complex to build that signoff has become something of a balancing act between what the verification teams believe is good enough and time-to market demands. Low-Power/High-Performance Engineering talked about this with Simbal Rafiq, director of engineering at Applied Micro; Robert Hoogenstryd, senior director of marketing for design analysis and signoff ... » read more

Verifying Complex Chips


System-Level Design talks about what's changing in SoC verification with Janick Bergeron, verification fellow at Synopsys; Harry Foster, chief verification scientist at Mentor Graphics; Pranav Ashar, chief technology officer at Real Intent; Raik Brinkmann, president and CEO of OneSpin Solutions, and Tom Anderson, vice president of marketing at Breker Verification Systems. [youtube vid=DzDYyf... » read more

FinFETs, EUV And Moore’s Law


GlobalFoundries VP Subramani Kengeri talks about progress and problems with advanced processes with Semiconductor Manufacturing & Design. [youtube vid=_Ang0I1vWdI] » read more

Tech Talk: Getting To The Next Node


IBM's Gary Patton talks with Low-Power/High-Performance Engineering about finFETs, EUV, and the challenges of staying on the Moore's Law road map. [youtube vid=jtz9XSXyBp0] » read more

ESL Challenges


System-Level Design talks about the challenges of ESL with Cadence's Ran Avinun, Synopsys' Johannes Stahl, Mentor Graphics' Thomas Bollaert and Forte Design Systems' Brett Cline.   [youtube vid=HftMM71Epqo] » read more

Roundtable: Battery Life Vs. Delay


Low-Power High-Performance Engineering talks about the challenges of dealing with latency in semiconductor design with Andrew Caples of Mentor Graphics, Chris Rowen of Tensilica, Drew Wingard of Sonics and Larry Hudepohl of MIPS Technologies. [youtube vid=Q_opQ3W9esA] » read more

Increasing Levels Of Risk


Semiconductor Manufacturing & Design sits down with Mentor Graphics' Jean-Marie Brunet to talk about double patterning, finFETs, design rules at advanced nodes and why design for manufacturing (DFM) has suddenly become so popular. [youtube vid=3GHvikyjZow] » read more

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