Challenges Increase for IP At Advanced Nodes

At advanced process nodes such as 16/14/10nm, designing is a much tougher nut to crack due to complexity and other considerations, not to mention then trying to migrate and/or re-use that IP. Still, engineering teams are looking for leverage wherever they can find it in their designs amid the technical challenges to overcome.

Tomasz Wojcicki, vice president of customer engineering support at Sidense, recalls that at one time it was possible to remember an entire design rule manual and that DRC didn’t need to be run to understand that the layout is correct because there were only 20 or 30 different design rules. “Right now, we don’t even read design rule manuals because they are just too complex to remember. That is obviously complicated. Another complication comes from things like finFET technology and the restrictions.”

Also, over the past year, advanced fabs have moved to production ramp of 20nm, and 16nm/14nm SoC chips, observed Hem Hingarh, vice president of engineering at Synapse Design. “In 2014 we have begun to see the development work across the ecosystem for 10/7nm. Going forward, finFET device structure will continue to dominate in 10nm and 7nm process technology. This advancement has its own challenges for IP and SoC development including: device structure and modeling; fixed width issue; device variability and lithography and its impact on physical design, with technology adoption and IP development. Specific lithography and physical design related issues include the fact that 20/16/14nm and below is basically the era of coloring, as far as double patterning and multi-patterning design. Customers are beginning to use new methodologies and implement their SoCs using new EDA tools, which has helped accelerate the learning curve.”

Designs at 16/14nm and below (10 and 7nm) require more advanced litho hotspot checking and more complex and accurate fill structures to help ensure planarity. Also, a finFET is a 3D device structure, which requires a more complex SPICE model, including a more accurate device extraction model. Using finFETs, designers have to worry about new sources of variability because the fin width has a significant impact on VT, and fin height creates width variability including 3D effects, quantization of device widths as wide devices are made out of multiple small width devices. Other impacts include a requirement for integer numbers of fins, changes in device parasitic R, C compared to planar devices, large G-S caps (Miller caps), S, D contact resistance and self-heating effects, Hingarh explained. “For 16/14nm FinFET based designs, since there are so many new device level issues, one has to start from scratch, even discarding the some of the ‘rules of thumb,’ which most designers have relied on for years with planar devices,” he said. “Because of these issues, designers of standard cell, memory, complex analog / mixed signal, including PLLs, ADCs, DACs, SerDes, and transceivers, will need to explore alternative architectures and circuit optimization techniques.”

Therefore, the IP must meet specifications across all PVT (process, voltage and temperature) conditions to take into account device effects. More extraction corners—about 15 to 20—have ve been added, which lengthen the simulation time. And as a result, IP designers have to perform many more effective circuit characterizations at the cell, block level and at the IP level to ensure that their designs meet rigorous requirements prior to delivery to their customers, Hingarh continued.

More than ever, engineering teams rely on accurate circuit simulation tools that are foundry-certified for technology and have the performance and capacity to handle complex circuits including physical effects such as complex parasitics, process variability and noise and self-heating. Specifically, in memory/register file applications, 16/14nm finFET technology will require more optimization work on sense (shunt) amplifier design—special purpose amplifiers that modify voltage according to the power rail current. “For high-performance and low-power memories, customers much more accurate timing and power models. We need simulation tools that can deliver SPICE-like accuracy in short time like current solutions,” he suggested.

Reuse depends on whether IP is soft or hard
When it comes to reuse, Kevin Yee, product marketing director for the IP Group at Cadence, said it really depends on whether the IP is hard or soft. “For the soft IP, it’s really process agnostic in general, so from a reuse perspective, changing process nodes really don’t make that much difference one way or another because you’re getting RTL generally and you’re going to synthesize it, do place and route, and everything else. From that perspective, does it get any harder/easier? It’s a ‘Don’t Care.’ But when it comes to hard IP, generally you’re going to get a GDS, so it really depends on how you define what the IP is. If I’m going to do an IP on, let’s say, 16nm finFET — which is the latest advanced node that most people are going to right now — essentially exact reuse, there’s no difference because my IP is defined as a DDR PHY on 16nm finFET. If someone else wants to use it, generally, there’s not going to be any difference because it’s a GDS.”

But moving from 28nm to 16nm involves IP porting or migration because it’s a completely different design. “From that perspective it is going to be much more difficult, more complex,” Yee said. “If you look at process nodes, 40nm was probably the last node that there was a lot of things that were common. You can jump from process to process, whether it’s TSMC or UMC or GlobalFoundries. When you got to 28nm, everything changed. Everyone tried to tweak their process a little bit. At that point, whether it is migration or IP reuse, it gets more difficult.”

At 16/14nm the challenges mount further thanks to technical requirements that must be reflected in the tools, Yee explained. “For example, at 28nm you had things like beginning of line/end of line, and that’s all having to do with metal stacks. In 14nm, they introduce a new one, which is middle of line, and double patterning. Then, at different processes, if you were moving from a GlobalFoundries 28nm versus a TSMC 28nm, GlobalFoundries started with a gate-first, versus TSMC, which is gate-last. This made it more difficult [to do IP migration across processes]. And then there are certain processes where you really can’t migrate at all—technically you can, but you’re almost starting from scratch. Say you were going from 28nm poly/SiON and you wanted to move to a 28nm high-k/metal gate. No one would really want to touch that because it’s almost a redesign. Technically we’re advanced enough to do it, but do you really want to? Is it worth it?”

The role of the IP provider
To help offset some of this complexity—particularly for integration and re-use—there is a fundamental shift happening in the IP industry to place more responsibility on the IP providers. According to Yee, at 90, 65/55 and 40nm, a lot of foundry enablement was in existence. “At that point, you could choose a foundry and it didn’t have a big impact on you. As you go to the more advanced nodes, that changes significantly because now it becomes more about foundry enablement: What do I have in place? We are seeing customers making decisions based on what’s available. Before, everything was available for any foundry and yes, it was difficult, but all the IP was in place at all the different nodes and processes. Today, you don’t have that. At 28nm, most people started their PDK development at 1.0, so things were kind of stable and mature. You developed your IP, it was already at a 1.0 PDK, you knew things weren’t going to change. Today, if you’re looking at 16/14/10nm and so on, people are starting their PDKs at 0.3, 0.5, which mean you know that things are going to change. You have to do a refresh of the IP, so the whole enablement is a little less mature. We see companies deciding what foundry and what process node they’re going to do based on what IP might be available, whereas before you just assumed the IP would be there.”

This translates to the IP supplier becoming a significant influencer in the entire process of choosing, since IP enablement is so critical.

From his perspective, Navraj Nandra, senior director of marketing for the DesignWare Analog and Mixed-Signal IP Solutions Group at Synopsys, said the issue with advanced nodes is not so much about reuse as getting right in the first place. “With each new process node, customers use this is as an opportunity to go to the next protocol generation, for example LPDDR3 to LPDDR4-3200, PCI Express 3.0 to PCI Express 4.0. Also, customers are integrating more complex interfaces on the smaller nodes. What this means is that the IP must fit the beachfront of the SoC. So the point is that with the smaller nodes, the IP architectures need to be re-designed to meet the next generation protocols and also support the digital scaling laws in terms of power, performance and area.”

In addition to the requirements detailed above, advanced nodes will demand that test data and diagnosis of test fail data play an increasingly important role in the production ramp of new 16/14nm finFET technologies, Hingarh said.

“There is need for new models and many tools. One such example is that because of finFET transistor structures, new memory cell fault models have to be added. Once 16/14nm methodology and tools are in place, scaling to 10nm technology will mainly require incremental upgrade in methodology and tools. The jury is still out, but 7nm may need a major transistor structural change away from silicon and will require new methodology and tools,” he concluded.